Reducing cache conflicts by multi-level cache partitioning and array elements mapping

NCUIR > College of Electrical Engineering & Computer Science > Graduate Institute of Computer Science and Information Engineering > journal & Dissertation > Item 987654321/32188

Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/32188

Title:	Reducing cache conflicts by multi-level cache partitioning and array elements mapping
Authors:	Chang,CY;Sheu,JP;Chen,HC
Contributors:	資訊工程研究所
Keywords:	LOOP
Date:	2002
Issue Date:	2010-07-06 18:20:40 (UTC+8)
Publisher:	中央大學
Abstract:	This article presents an algorithm to reduce cache conflicts and improve cache localities. The proposed algorithm analyzes locality reference space for each reference pattern, partitions the multi-level cache into several parts with different sizes, and t
Relation:	JOURNAL OF SUPERCOMPUTING
Appears in Collections:	[Graduate Institute of Computer Science and Information Engineering] journal & Dissertation

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