智慧型高畫質視訊縮放器的設計與實作 ; Design and Implementation of an Intelligent HD Video Scaler

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题名:	智慧型高畫質視訊縮放器的設計與實作;Design and Implementation of an Intelligent HD Video Scaler
作者:	張廖元超;Yuan-chao Chang Liao
贡献者:	資訊工程學系碩士在職專班
关键词:	機率式神經網路;縮放器;管線化架構;影像插補器;scaler;PNN interpolation;interpolator;pipeline
日期:	2010-07-28
上传时间:	2010-12-09 13:49:57 (UTC+8)
出版者:	國立中央大學
摘要:	高解析顯示已經成為多媒體播放的主流，但由於目前流通的視訊內容多數並非以高解析畫質為前提製作，利用縮放器將輸入視訊放大以提高解析度是現今常見的解決方案，而縮放器的核心即為影像插補器。本研究發展了一個基於機率神經網路插補器的智慧型視訊縮放器。此一插補器分析影像中每一個插補點周圍區域的銳利度，根據銳利度的評估值作為單神經元的輸入去調整PNN插補器的平滑參數，最後以此PNN插補器進行插補運算。基於PNN插補器的視訊縮放器具有適應不同影像區域的插補特性，在邊緣附近得以產生高銳利度的插補效果，而在平滑區域，則可產生加強平滑的插補效果。相較於傳統視訊縮放器，本系統展現十分優異的縮放後的影像品質。這個智慧型視訊縮放器於FPGA實驗平台上驗證了其功能的正確性和性能。除了實作了PNN影像插補器硬體電路，我們還完成了記憶體控制器、液晶顯示控制器、影像處理器，最後設計一個管線化控制器，將各硬體模組整合成平行架構的視訊縮放晶片。本晶片僅使用了2147 Logic Elements和241k bits記憶體FPGA硬體資源，並可達到每秒30 frames 1920x1080影像的插補速度，顯示本系統具有令人滿意的性能。本研究成果將可以應用在數位電視、視訊監控與可攜式高畫質媒體播放裝置等。High- definition display has become the mainstream of media player, but most of the current distribution of video content is not premise of making High-definition video quality, using scaler to enlarge the input video resolution is a common solution today, the core of scaler shall be interpolator. This paper developed a probabilistic neural network-based intelligent video interpolator. This interpolator analysis of image in the region around the each interpolation point sharpness, according to the evaluation value of sharpness as a single neuron input to adjust the smoothing parameter of PNN interpolator, finally using PNN interpolator to do it. The probabilistic neural network-based intelligent video interpolator has to adapt to different characteristics of video interpolation region, it provides more sharp effect near the edge, and in the smooth region, to enhance smooth effect is provide. Compared with conventional video scaler, the system shows a very excellent scaled image quality. This intelligent video scaler has verified its functional correctness and performance in the FPGA test platform. Apart from implement PNN interpolator hardware circuit, we also completed the memory controller, LCD controller, image processor, finally design a pipeline controller for each of the parallel hardware architecture module integrated into the video scaling chip. The chip uses only 2147 Logic Elements and 241k bits of memory on FPGA hardware resources, and can reach 30 frames 1920x1080 images per second interpolation rate, indicating the system has satisfactory performance. The research results will be used in digital television, high-definition video surveillance and portable media player devices.
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