內容定址記憶體之三維架構探索與測試 ; Three-Dimensional Architecture Exploration and Testing of Content Addressable Memories

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题名:	內容定址記憶體之三維架構探索與測試;Three-Dimensional Architecture Exploration and Testing of Content Addressable Memories
作者:	胡詠鈞;Yong-Jyun Hu
贡献者:	電機工程研究所
关键词:	三維架構;三維積體電路;內容定址記憶體;測試演算法;記憶體測試;錯誤模型;可靠性設計;3-D IC;content addressable memory;test algorithm;fault model;memory testing;design-for-reliability
日期:	2010-05-27
上传时间:	2010-12-09 13:50:00 (UTC+8)
出版者:	國立中央大學
摘要:	三維積體電路之晶片設計 (3-D IC design) 技術，已被公認是一項可行的晶片設計技術。相較於現今二維積體電路，三維積體電路的優點在於小外觀 (small form factor，SFF)、高效能、高功能性、及低功率消耗。三維積體電路技術非常適合應用於具有規律特性的記憶體電路，這其中就包括內容定址記憶體 (content addressable memory，CAM)。內容定址記憶體目前已廣泛地應用在數位系統中，包括網路應用、密碼學 (cryptography)、資料壓縮、及快取記憶體等。如何提升內容定址記憶體的效能及降低其功率消耗是設計內容定址記憶體時的兩大關鍵。內容定址記憶體的最小單元包含了儲存單元和比較器兩部份，以致於它可以實現其平行比對 (parallel comparison)的功能，但也造成它的面積和複雜度比一般的靜態隨機存取記憶體 (SRAM) 還要高很多。因此，當設計一個大儲存容量的內容定址記憶體，可利用三維積體電路的技術來進一步提升其速度並降低其能量消耗及面積腳位。在論文的第一部份提出了三種擁有三維架構的內容定址記憶體和優先權位址編碼器 (priority address encoder，PAE)，分別為搜尋線分割 (searchline-partitioned) 三維內容定址記憶體架構、命中線分割 (matchline-partitioned) 三維內容定址記憶體架構、及搜尋線-命中線混合分割(searchline-matchline hybrid-partitioned) 三維內容定址記憶體架構 (以下分別簡稱SPCAM3D、MPCAM3D、及SMHPCAM3D)。實驗結果顯示，假設在搜尋線大小為1024單位、雙層晶粒 (die) 堆疊的情況下，SPCAM3D架構可使內容定址記憶體的搜尋時間比二維架構時降低29.13%；而假設在命中線大小為128-位元、雙層晶粒堆疊的情況下，MPCAM3D架構可使內容定址記憶體的搜尋時間比二維架構時降低23.21%；而假設在記憶體大小為1024x128-位元、四層晶粒堆疊的情況下，SMHPCAM3D架構可使內容定址記憶體的速度比二維架構時提升最多66.78%。除此之外，我們也提出了兩種應用了前看 (lookahead) 及折疊 (folding) 技術的三維架構優先權位址編碼器，且實驗結果顯示在大小為1024-128位元、雙層晶粒堆疊的情況下，相較於傳統的二維架構之優先權位址編碼器，可分別降低45.78%和42.35%的關鍵延遲時間 (critical delay time)。最後，我們提出可重新裝配 (reconfigurable) 之內容定址記憶體架構，在單一顆晶粒時可實現二元內容定址記憶體 (binary CAM) 之功能；而當複數顆的晶粒運用三維技術堆疊之後，則可實現三元內容定址記憶體 (ternary CAM) 之功能。論文的第二部份則針對擁有非對稱性單位結構 (asymmetric cell structure) 之三元內容定址記憶體，我們定義並模組化它在執行比較 (Compare) 動作時可能發生的比較錯誤 (comparison fault)。為了有效測得所定義的比較錯誤，我們提出兩個類行軍式 (march-like) 測試演算法，分別為TACHit和TACPAE。當測試一個大小為NxB-位元之非對稱性且只擁有擊中結果輸出器 (Hit output) 的三元內容定址記憶體時，可使用TACHit測試演算法進行測試。此時需要執行8N次寫入 (Write) 動作及3N+2B次比較動作來測得100%所定義之比較錯誤。而當測試一個大小為NxB-位元之非對稱性且擁有擊中結果輸出器和優先權位址編碼器的三元內容定址記憶體時，則可執行TACPAE測試演算法進行測試。此時只需要執行4N次寫入動作及3N+2B次比對動作來測得100%所定義之比較錯誤。論文的最後部份則針對SPCAM3D與MPCAM3D兩個三維內容定址記憶體架構提出測試方案。兩種內建自我測試 (built-in self-test，BIST) 電路加上平行測試介面 (parallel test scheme) 分別被提出。兩種測試方案可配合二維內容定址記憶體的類行軍式測試演算法，來更有效率地測試前述SPCAM3D與MPCAM3D兩種三維內容定址記憶體架構中的比較錯誤。進一步分析及比較的結果可得知，由於平行測試介面的關係，兩種測試方案可以有效地降低測試複雜度。Three-dimensional (3-D) integrated chip (IC) design technology is now widely acknowledged as one of the future chip design technologies. A 3-D IC has many benefits over a conventional 2-D IC, such as small form factor, high functionality, high performance, and low power consumption. Due to the regularity of a memory circuit, it is a very good candidate for 3-D technology. Content addressable memories (CAMs) are widely used in digital systems, such as networking, cryptography, compression, cache memory, etc. How to improve the performance and reduce the power of the CAM are two of key design issues. On the other hand, the area of a CAM cell is much larger than that of an SRAM cell because of that a CAM cell consists of a storage element and a comparator for executing parallel comparison. Therefore, if a large-capacity CAM is needed, then the footprint of the CAM is very large. 3-D integration technology can be used to reduce the power and the footprint of a large-capacity CAM. In the first part of this thesis, three 3-D architectures for the CAM and priority address encoder (PAE) are proposed. The first is the Searchline-Partitioned 3-D CAM architecture (SPCAM3D), and the second is the Matchline-Partitioned 3-D CAM (MPCAM3D) architecture, and the third is the Searchline-Matchline Hybrid-Partitioned 3-D CAM (SMHPCAM3D). Moreover, a 3-D PAE with lookahead and folding techniques is introduced. Compared with the 2-D CAM architecture, simulation results show that the proposed SPCAM3D architecture with two 3-D layers gets about 29.13% improvement on search time when the number of words of the CAM is 1K; the MPCAM3D architecture with two 3-D layers gets about 23.21% improvement on search time when the word width of the CAM is 128; and the SMHPCAM3D architecture with four 3-D layers gets 66.78% performance improvement when the configuration of the CAM is 1K×128 bits. For the proposed 3-D PAE and 3-D folding PAE with two 3-D layers, simulation results show that they can provide 45.78% and 42.35% performance improvement, respectively, on critical delay time in comparison with the 2-D PAE if the size of PAE is 1K-bit. Finally, a reconfigurable CAM architecture for realizing a binary CAM or ternary TCAM is proposed. The reconfigurable CAM architecture can be implemented in a die as a binary CAM. On the other hand, one can stack multiple reconfigure CAM dies to realize a ternary CAM. In the second part of this thesis, the comparison faults of ternary CAMs with asymmetric cells are defined first. Then, two march-like test algorithms are proposed to cover the defined comparison faults. The first test algorithm TACHit requires 8N Write operations and (3N+2B) Compare operations to detect 100% comparison faults for an N×B-bit TCAM with asymmetric cells and Hit output only. The second test algorithm TACHit requires 4N Write operations and (3N+2B) Compare operations to detect 100% comparison faults for an N×B-bit TCAM with asymmetric cells and Hit and PAE outputs. In the last part of this thesis, test procedures for CAMs with the SPCAM3D and the MPCAM3D architectures are presented. A built-in self-test (BIST) scheme is proposed to test CAMs with SPCAM3D architecture. On the other hand, a BIST scheme is proposed to test CAMs with MPCAM3D architecture. Both the BIST schemes for 3-D CAMs can generate the March-like test algorithms for 2-D CAMs. The experimental results shows that the test time of 3-D BISTs for SPCAM3D and MPCAM3D are only 51.21% and 79.07%, respectively, of the test time of 2-D BIST.
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