垂直式與平面式結構單電子電晶體之研製與特性分析 ; Fabrication and Electrical Characterizations of Single Electron Transistor in Vertical and Planar Structures

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Title:	垂直式與平面式結構單電子電晶體之研製與特性分析;Fabrication and Electrical Characterizations of Single Electron Transistor in Vertical and Planar Structures
Authors:	黃郁婷;Yu-Ting Huang
Contributors:	電機工程研究所
Keywords:	單電子電晶體;Single Electron Transistor
Date:	2010-07-23
Issue Date:	2010-12-09 13:53:11 (UTC+8)
Publisher:	國立中央大學
Abstract:	單電子電晶體因具有高電荷靈敏度以及低消耗功率的潛能優點而被受矚目，且被認為在未來可應用於記憶體、邏輯電路以及量子電腦的發展。本論文針對垂直式與平面式的鍺量子點單電子電晶體結構的研製以及電流特性分析做探討。目前本研究團隊已可在在複晶矽鍺的孔洞中利用氧化來達到鍺量子點的定位與定量。我們可藉由低壓化學氣相沉積系統能夠精準控制薄膜厚度的優點沉積二氧化矽與氮化矽側壁的穿隧介電層，並使元件中的鍺量子點自動對準到電極。進而改善自我對準電極元件因電子束微影曝寫時造成奈米線抖動而無法掌控量子點位置與穿隧介電層厚度的缺點。Single-electron transistors （SETs） have attracted a lot of attention for its potential advantages of high charge sensitivity and low power consumption, which would offer great potentials for memory-devices, logic-devices and quantum computing in the future. In this thesis, we have studied the fabrication and electrical characterization of Ge QD SETs in vertical and planar structures. We are able to bridle the position and the number of Ge QDs by oxidizing poly-SiGe in a nano-cavity. The Ge QDs are self-aligned to adjacent electrides via SiO2 or Si3N4 spacers, which also behave as tunnel barriers and whose thickness are directly determined by the thin-film deposition in CVD.
Appears in Collections:	[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

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