三維系統級封裝晶片之記憶體的測試與修復 l; Testing and Repair of Memories in 3D-SiP Chips

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Title:	三維系統級封裝晶片之記憶體的測試與修復 l;Testing and Repair of Memories in 3D-SiP Chips
Authors:	陳亭如;Ting-Ju Chen
Contributors:	電機工程研究所
Keywords:	診斷資料壓縮;記憶體內建自我修復;記憶體內建自我測試;Memory Built-In Self-Test;Memory Built-In Self-Repair;Diagnostic Data Compression
Date:	2010-08-27
Issue Date:	2010-12-09 13:55:22 (UTC+8)
Publisher:	國立中央大學
Abstract:	對於整合不同製程的元件，系統級封裝 (System-in-Package, SiP) 整合技術將為其有效的解決方法。在典型的系統級封裝晶片中，不同類別的裸晶將透過打線 (bonding wire) 相互堆疊和連接。其中，記憶體裸晶為廣泛使用的裸晶之一。不同類別的記憶體裸晶都可能整合於一個系統級封裝晶片中。然而，由於大部分記憶體裸晶的輸入/輸出腳位都無法直接透過封裝晶片的輸入/輸出腳位做存取，倘若在後封裝階段 (post-packaging phase) 欲使用自動測試設備 (external automatic test equipment, ATE) 測試這些記憶體裸晶將非常困難。因此，發展應用於後封裝階段有效的測試技術為必要的。顯然地，在系統級封裝設計上內建自我測試 (built-in self-test, BIST) 技術為測試記憶體裸晶的有效方法。論文的第一部分，提出一個可程式化的內建自我測試方法用於測試系統級封裝晶片中系統晶片 (System-in-Chip, SoC) 裸晶的 SRAM、Flash 記憶體裸晶和 SDRAM 裸晶。在 SDRAM 的測試上，提出一個測試程序用以有效的降低記憶體的測試時間。並且，提出一個應用於 SDRAM 執行突爆模式 (burst mode) 測試時，特定的測試診斷方法。所提出可程式化內建自我測試方法具有高測試診斷能力、高可攜性、可平行測試和低測試複雜度的優點。由實驗結果觀察可知，在系統晶片具有兩個 SRAM (512K-bit SRAM 和 1M-bit SRAM) 和一個 256M-bit Flash 裸晶的情形下，所提出可程式化內建自我測試電路的面積涵蓋率只為 0.07%。論文的第二部分，提出一個可改變取樣大小的適應性徵狀壓縮演算法，將有效降低診斷資料輸出時間和 ATE 的儲存容量。由實驗結果觀察可知，在系統級封裝晶片中所提出可程式化內建自我測試電路結合上適應性徵狀壓縮器，在系統晶片具有兩個 SRAM (512K-bit SRAM 和 1M-bit SRAM) 和一個 256M-bit Flash 裸晶的情形下，電路的面積涵蓋率只為 0.08%。論文第三部分，提出一個可重組的內建備份元件分析器 (built-in redundancy analyzer, BIRA)，所提出的方法只需一次測試流程且使用非常低的面積成本達到最佳修復效率。此外，提出的層級式緩衝器將用來萃取錯誤字組中多個錯誤位元，如此，便能支援字組導向記憶體執行同速測試與備份元件分析。由實驗結果觀察可知，所提出可重組內建備份元件分析方法在實現上面積成本較現存方法低。System-in-Package (SiP) integration technology provides a good solution for integrating components with different technologies. In an SiP, typically, various types of dies are stacked and connected with bonding wires. Among those dies, memory die is one widely used die. Furthermore, different types of memory dies may be integrated in the SiP. Using external automatic test equipment (ATE) to test these memory dies in the post-packaging phase becomes very difficult, since the I/O terminals of most of these memory dies cannot be directly accessed through the I/O pins of the package. Effective test techniques for testing these memory dies in the post-packaging phase thus should be developed. Apparently, built-in self-test (BIST) technique is a good solution for testing the memory dies in SiP designs. In the first part of this thesis, a programmable BIST scheme is proposed to test the SRAMs in a System-on-Chip(SoC) die, Flash memory dies, and SDRAM dies in an SiP chip. For the testing of SDRAMs, an efficient test procedure is proposed to reduce the testing time. Also, a specific diagnosis approach is proposed to diagnose the SDRAM when it is tested in burst mode. The proposed BIST scheme has the advantages of high diagnosability, high portability, parallel test, and low test complexity. Experimental results show that the area overhead of the proposed BIST circuit for one 512K-bit SRAM and one 1M-bit SRAM in an SoC die, and one 256M-bit Flash die is only about 0.07%. In the second part of this thesis, an adaptive syndrome compression algorithm for variable-size symbols is proposed to reduce the diagnostic data exportation time and the storage requirement of ATE. Experimental results show that the area overhead of the proposed BIST circuit with the adaptive syndrome compressor for an SiP with one SoC die in which one 512K-bit SRAM and one 1M-bit SRAM are embedded, and one 256M-bit Flash memory die is only about 0.08%. In the third part of this thesis, a reconfigurable built in redundancy analyzer (ReBIRA) scheme which can provide the optimal repair efficiency using very low area cost and one test run is proposed. In addition, a level- based buffer is proposed to extract multiple-bit failure of a faulty word to support the at-speed test and redundancy analysis for word-oriented RAMs. Experimental results show that the area cost for implementing the proposed ReBIRA scheme is much lower than that of existing works.
Appears in Collections:	[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

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