兼併切換式電容及切換式放大器且應用於生醫訊號之三角積分調變器 ; A Sigma-Delta modulator for Bio-signals Measurement System Combining Switched-Capacitor and Switched-OPAMP Technique

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Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/44798

Title:	兼併切換式電容及切換式放大器且應用於生醫訊號之三角積分調變器;A Sigma-Delta modulator for Bio-signals Measurement System Combining Switched-Capacitor and Switched-OPAMP Technique
Authors:	林妤穎;Yu-ying Lin
Contributors:	電機工程研究所
Keywords:	切換式電容;switched-opamp;switched-capacitor
Date:	2010-10-22
Issue Date:	2010-12-09 13:55:54 (UTC+8)
Publisher:	國立中央大學
Abstract:	近年來，憑藉著醫學與超大型積體電路的演進，常見的生理訊號量測儀器已朝向多功能、可攜式與高精準度發展。在量測系統中，除低雜訊生醫放大器外仍需一高精密度之類比數位轉換器將訊號正確地交由數位訊號處理模組進行資料處理與分析。因此，本論文中選擇三角積分調變器 (SDM) 之類比數位轉換器，其可降低前端類比濾波器設計之困難與功率消耗，進而減少整體量測系統面積。三角積分類比數位轉換器主要由三角積分調變器與數位降頻濾波器所組成。本文所設計之電路結合SC-SDM與SO-SDM之優點並將其整合，以低功率與高解析度為其設計標的完成一應用於所有生理訊號量測之三角積分調變器。電路實現上，在訊號頻寬10KHz、128倍超取樣率與±0.1V的輸入振幅下，所設計之二階三角積分調變器訊號雜訊失真比為70.5dB，有效位元數達到11.7位元且整體晶片消耗之功率為161μW。製作過程使用台積電0.18μm CMOS 1P6M製程，其晶片面積約佔1.035mm2。最後的量測結果顯示訊號雜訊失真比為46.2dB，有效位元數為7.7位元。在1.8V電源供應下，整體晶片消耗之功率約224μW。In recent years, public bio-signal measurement systems have been developed toward high accuracy, multi-functionality and portability due to the advancement of the medical science and VLSI technology. In addition to the bio-signal analog-front-end (AFE) circuits, measurement systems require a precision analog-to-digital (A/D) converter that can convert signals precisely to digital signal processing for analyzing data. Therefore, we choose the A/D converter which include Sigma-Delta modulator (SDM) to reduce anti-aliasing filter complexity and power consumption, resulting in reducing overall chip area of measurement systems. A Sigma-Delta A/D converter mainly consists of SDM and decimation filter. In this thesis, the proposed SDM combines the advantages of Switched-Capacitor SDM (SC-SDM) and Switched-OPAMP SDM (SO-SDM). The SDM aiming at low power consumption and high resolution is accomplished for all applications of bio-signal measurement. The modulator achieves 70.5dB signal-to-noise and distortion ratio (SNDR), 11.7 effective number of bits (ENOB) , and power consumption 161μW at 10-KHz signal bandwidth with an oversampling ratio (OSR) of 128, and 0.2Vp-p amplitude. The circuit is fabricated in the TSMC 0.18-μm one-poly six-metals CMOS process, and chip area is 1.035mm2. Finally, the measurement results show that signal to noise distortion ratio is 46.2dB, and 7.7 effective number of bits. The measured power consumption is about 224μW for 1.8V power supply.
Appears in Collections:	[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

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