應用於電容陣列區塊之維持比值良率的通道繞線法; A Yield-aware Ratio-keeping Channel Router for Capacitor Array Block Creation

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题名:	應用於電容陣列區塊之維持比值良率的通道繞線法;A Yield-aware Ratio-keeping Channel Router for Capacitor Array Block Creation
作者:	曾煥程;Huan-cheng Tseng
贡献者:	電機工程研究所
关键词:	良率;比值;佈局自動化;layout automation;yield-aware;ratio-keeping
日期:	2010-11-03
上传时间:	2011-06-04 16:13:08 (UTC+8)
出版者:	國立中央大學
摘要:	隨著半導體製程技術的演進，製程變動(process variation)所造成元件之間的不匹配(mismatch)與導線寄生效應(parasitic effect)的相對應變異也越來越嚴重。然而在類比電路上為了降低設計時的高錯誤率、高複雜度及容易出錯的佈局操作所花費的時間與繁瑣的任務和昂貴的設計成本，所以佈局的自動化設計將成為類比設計過程中一個關鍵的角色。且由於敏感的寄生電容效應、元件的不匹配、製程變動與梯度效應都將導致佈局結果可能是一個不好的佈局，也造成了產品的不準確性與良率的降低。多數類比電路像是類比數位/數位類比轉換器或濾波器等等，其性能都依賴於準確的電容比值。對於要求準確的電容比值大都會使用多顆單位電容並聯取代單一顆大電容並考慮繞線引起的寄生效應，以減少一些不匹配的影響。本論文中提出一種維持比值良率的繞線方法在電容陣列佈局的應用上。透過四個步驟分別為通道分配、導線建立、導線連接與極板伸出，以進行平衡導線的繞線長度與電容導線上相對應的via個數和減少由於交錯或重疊的寄生電容。對於多個特定電容所組成的電容陣列此繞線也能自動化實現完成。這裡舉出兩個例子藉由空間相關性提供的電容陣列的擺放結果來說明繞線的過程與影響。一個是由兩個特定電容組成的陣列其比值為1:1，而另一個陣列是由多個特定電容組成其比值為1:2:16:45。佈局完成後透過Calibre萃取寄生電容並送入SPICE做驗證，結果顯示電容比值的準確度是非常接近所要求的。最後用一個交換式電容電路其電容值分別為3pF、4pF和5pF來介紹繞線後對比值偏移的補償方式及重新調整部分單位電容之參數以藉此將良率提高。 As the evolution of semiconductor process technology, the process variation will be more and more serious in device mismatch and wire parasitic. Layout automation is likely to play a key role in analog circuit design to prevent design errors, high complex, error-prone layout tasks, time-consuming, tedious and expensive design iterations. Poor layout due to its sensitivity to parasitic capacitance, device mismatching, process variations and gradient errors will result in both the product inaccuracy and yield loss. The performance of many types of analog circuits, like ADC, DAC, filters, etc., relies on the implementation of accurate capacitor array ratios, which are determined by properly arranging the identical unit-size capacitors and considering the effect of routing induced capacitances. In this thesis, a yield-aware ratio-keeping channel router is proposed for capacitor array block creation. The 4-step channel router including channel allocation, wire establishment, wire link, and plate outstretching, is performed ordinarily to balance the routing wire length and the number of wire contact via’s of the corresponding array capacitors and to reduce the parasitic capacitances due to extra insertions and overlapping. The router can be not only applied to the case of a pair of two target capacitors but also to the one of multiple target capacitors. By the conjunction of an array assignment using of spatial correlation feature, two cases are used as examples to demonstrate the array assignment-routing flow. One is a case of two targets with a ratio of 1:1 and another is a case of multiple targets with continuous ratio of 1:2:16:45. It is shown that both the final results are very close to the desired, where the target and parasitic capacitances are extracted from post-layouts by Calibre and they are fed into SPICE to verify the desired ratios. A switched-capacitor filter with three target capacitors of the values of 3 pF, 4 pF and 5 pF is used to leverage the compensation effect for yield improvement by re-adjusting the fraction of unit-capacitor after routing.
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