典型的固態硬碟控制器多採用處理器作為快閃記憶體管理之核心，以執行FTL中介軟體(middleware)。FTL演算法主要目標在於有效管理快閃記憶體，這些演算法通常具有很高的計算複雜度，使得處理器難以負荷，或者使用更高速的處理器導致耗電和成本攀升。本論文所提出的固態硬碟控制器，是將FTL演算法設計成高效能的硬體核心，以實現一個不需要使用處理器的高速硬體化固態硬碟控制器，以硬體加速的方式縮短運行演算法時所耗費的時間，藉此來提高整體控制器的性能，同時可以降低功耗。 我們以階層式和模組化的系統化設計方法來進行此一複雜演算法的硬體設計，同時採用GRAFCET建模來描述每一模組的離散事件行為，最後將其合成為VHDL-based硬體IP，並於FPGA平台進行實體驗證，以此硬體化固態硬碟控制器整合到現有的固態硬碟系統架構中，實驗證明，相對於使用8位元處理器的FTL控制器，我們的系統可縮短整體存取時間33%，同時可以降低29%的功耗。 A typical Solid-State Disk controller usually uses a processor as the core of flash memory management that can execute Flash Translation Layer middleware. The purpose of FTL algorithm is to manage flash memory effectively. Generally, these algorithms which have high computational complexity cause the processor difficult to load. Some use the high performance processor to put up with the complexity of algorithms, which will lead to increasing power consumption and cost. The Solid-State Disk controller that this paper proposes is design FTL algorithm to be a core of high performance hardware to achieve a high speed hardware-based Solid-State Disk controller. With this method, it can decrease the time in running the algorithm to improve the performance of the controller while reducing power consumption. We use hierarchical and modular system design method to design the hardware of the complex algorithm, and meanwhile we use GRAFCET modeling to describe the behavior of discrete event of each module. Finally we synthesize the design to VHDL-based hardware intelligent property and verify it on FPGA platform, integrating this hardware-based Solid-State Disk controller into the existing Solid-State system architecture. The experiments show that compared with the controller that uses 8-bit processor to run FTL algorithm, our system can reduce 33% of the access time and 29% of power consumption.
