電力線通訊環境下即時OFDM傳收器之FPGA設計與實現; Design and FPGA Implementation of a Real-Time OFDM Transceiver for Power Line Communications

NCUIR > College of Electrical Engineering & Computer Science > Graduate Institute of Communication Engineering > Electronic Thesis & Dissertation > Item 987654321/48395

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Title:	電力線通訊環境下即時OFDM傳收器之FPGA設計與實現;Design and FPGA Implementation of a Real-Time OFDM Transceiver for Power Line Communications
Authors:	姜智強;Jhih-ciang Jiang
Contributors:	通訊工程研究所
Keywords:	正交分頻多工;電力線通訊;Power Line Communications;Transceiver;OFDM
Date:	2011-10-20
Issue Date:	2012-01-05 14:53:22 (UTC+8)
Abstract:	電力線通訊是藉由現有的電力線來當作媒介進行寬頻網路資料傳輸，不需要另外鋪設網路線路，可節省佈線成本。在本論文中，我們設計並實現了即時OFDM傳收器用於平台之傳收。在平台部分主要包含商用DAC/ADC EVM Board、電力線耦合電路及FPGA實驗板。在即時OFDM傳收器之數位訊號處理模組中，我們設計了OFDM訊號同步器、FFT處理器、通道估測/等化器、硬式決策器、訊號解交織器及通道解碼器在FPGA板子上。傳送之訊號頻段範圍2.3MHz~20MHz。在利用迴旋碼編碼率1/2的情況下，使用64-QAM調變能滿足傳輸資料率42.5Mbps。 Power line communication (PLC) system, which adopts the power line network as the transmission medium, enables broadband internet access across the house through existing AC electrical wiring. In this thesis, we design and implement a real-time OFDM transceiver for power line communications on a platform which consists of off-the-shelf digital-to-analog/analog-to-digital converters (DAC/ADC), power line coupling circuit and an FPGA board. The digital signal processing units required for the real-time OFDM transceiver, which includes OFDM symbol synchronizer, FFT processor, channel estimator/equalizer, hard decision logics, symbol/bit deinterleaver and viterbi decoder, is implemented on the FPGA. The spectral range of the transmitted signal is specified to be from 2.3MHz to 20MHz. With 64-QAM modulation and a convolutional code of code rate 1/2, the throughput of the transceiver system is around 42.5Mbps.
Appears in Collections:	[Graduate Institute of Communication Engineering] Electronic Thesis & Dissertation

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