本論文的研究為，利用選擇性氧化矽鍺方法，來製作嵌入於介電材料如二氧化矽或氮化矽中的多重鍺量子點陣列薄膜。藉由鍺量子點的低維度特性與其周圍介電材料的改變，形成一個具有低熱傳導率的薄膜，並量測其熱傳導與電傳導特性，作為日後發展熱電元件的基礎。 在薄膜熱傳導率的量測上，我們利用穩態熱傳導量測法，來進行熱氧化之二氧化矽、 氮化矽（低壓化學氣相沉積）、嵌入於二氧化矽的鍺量子點陣列、與嵌入於氮化矽的鍺量子點陣列薄膜熱傳導率量測，其薄膜的厚度約在數十到數百奈米之間。由量測的結果發現，當嵌入多重鍺量子點陣列於二氧化矽或氮化矽等介電材料中時，可有效地降低熱傳導率，其熱傳導率在溫度為78 K到430 K之間約0.2到0.8 W/mK左右，相較於二氧化矽薄膜（室溫約1 W/mK）與氮化矽薄膜（室溫約1-2 W/mK）的熱傳導率還更低。 在薄膜電傳導率量測方面，我們利用離子佈植技術將磷離子掺入於多重鍺量子點陣列薄膜中，來提升薄膜的導通電流與電傳導率。我們發現經由離子佈植後的薄膜，其電傳導率約可提升2到3個數量級。 The study of this thesis is that using the method of selective oxidation of SiGe, to form multi-layered Ge quantum dots (QDs) array embedded in dielectric thin film such as SiO2 or Si3N4. By use of the low dimensional property of Ge QD itself and changing the ambient materials, we can produce thin film which the thermal conductivity is very low. We also measured the thermal conduction and electrical conduction properties of these Ge QDs thin films, and this is the foundation of developing thermoelectric devices in the future. For thermal conductivity measurement, we use the steady state method to measure thermal SiO2, LPCVD Si3N4, Ge QDs array embedded in SiO2, and Ge QDs array embedded in Si3N4 thin film. The thickness of these thin films is in the range between tens and hundreds of nanometer. According to the measurement result, we’ve found that it can reduce the thermal conductivity effectively as Ge QDs array is embedded in dielectric such as SiO2 and Si3N4, and the thermal conductivity is approximately 0.2 to 0.8 W/mK at the temperature from 78 K to 430 K. This result is much lower than pure SiO2 and Si3N4 thin film, which the thermal conductivity is near 1 and 1-2 W/mK respectively at room temperature. For electrical conductivity measurement, we have doped phosphorous ions into the multi-layered Ge QDs array by implantation to enhance the conducting current and the electrical conductivity. We have found that the electrical conductivity is increased by about 2 to 3 orders after implanted.
