因為IC內部電晶體數目快速的成長，單一晶片中已經可以容納完整的電路系統，包含數位及類比電路。在混合訊號的設計中，因為外在環境訊號是連續的關係，所以類比部分是無法避免的。目前數位電路的自動化軟體工具已經發展得相當成熟，然而，類比混合訊號自動化設計工具並不是相當常見，主要是因為類比電路非常敏感，很難實現最佳化的工具。因此，類比電路設計往往成為整個混和訊號SOC發展的瓶頸。 佈局的擺置對於類比及混合訊號IC電路效能有很大的影響，因此擺置的結果非常重要。為了得到高效能的電路佈局，必須考慮許多佈局擺置的特殊限制，這也是為什麼類比電路佈局還無法完全自動化的原因。至今類比電路大都還是由工程師手工佈局為主，需要花相當多時間才能完成整個設計。因此要加速整個設計過程，輔助設計工具是不可或缺的。本論文是以一個鎖相迴路為實驗電路，提出一個自動化佈局設計工具。此工具支援特別的佈局限制及使用者提供的佈局樣板。整套流程已經以C++及Tcl/Tk程式語言實現，且自動化佈局的過程能在Laker環境下執行。本論文之自動化佈局工具，產生之佈局不僅可成功的通過DRC與LVS的驗證，Post-layout的模擬結果也能達到預期的電路效能。 Due to the fast growth of IC capacity, all of the circuits in a system can be integrated into a single chip, including digital and analog parts. The analog portion in the mixed-signal design is inevitable due to the nature of continuous signals in the external environment. Up to now, CAD tools in digital domain have been well developed. However, analog CAD tools are still not popular yet because analog circuits are very sensitive and hard to optimize. As a result, analog circuits become the bottleneck for the mixed-signal SOC design. In analog and mixed-signal IC layout, the placement phase is very critical because the quality of the resulting placement has great impacts on circuit performance. To obtain high-performance layout, we must consider many special layout constraints. That’s why the layout of analog circuit is far from automation. Most of analog circuit layouts are still manual which takes large amount of time to complete the whole design process. In this paper, we present an automatic layout design system for PLL circuits. Special layout constraints and user-provided layout template are support in our work. With the implemented C/C++ and Tcl/Tk programs, the layout automation process can be achieved in the Laker environment. The generated layout can pass DRC and LVS verification. The post-layout simulations also show a good consistency to the predicted performance, which demonstrates the success of this work.
