應用fT倍頻電路與被動結合器技術於低功率消耗毫米波混頻器之研究; The Study on fT-Doubler and Passive Combiner Techniques for Low Power Millimeter-Wave Mixer Designs

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題名:	應用fT倍頻電路與被動結合器技術於低功率消耗毫米波混頻器之研究;The Study on fT-Doubler and Passive Combiner Techniques for Low Power Millimeter-Wave Mixer Designs
作者:	梁嘉仁;Jia-Ren Liang
貢獻者:	電機工程研究所
關鍵詞:	被動結合器;低功率消耗;fT倍頻電路;毫米波混頻器;Low Power;Millimeter-Wave Mixer;fT-Doubler;Passive Combiner
日期:	2011-08-03
上傳時間:	2012-01-05 14:57:02 (UTC+8)
摘要:	本論文主要設計混頻器電路，論文主題分為兩大部分，第一部分使用tsmcTM CMOS 90 nm製程，設計“60 GHz低功耗雙平衡閘極驅動混頻器利用被動結合器技術”，電路架構主要利用被動結合器並使用基底耦合，將射頻與本振訊號相加，並輸入至CMOS電晶體閘極，利用電晶體平方律原理達到混頻，且利用雙平衡架構提升各埠隔離度。量測時本振功率1 dBm時，可得到轉換增益為3.4 dB，輸入功率1-dB壓縮點為-5 dBm，輸入三階交互調變失真點為6 dBm，本地振盪源至射頻與中頻隔離度皆大於33 dB，射頻至中頻隔離度大於27 dB，核心電路功率消耗只需0.9 mW，電路面積0.63 mm2。第二部分為fT倍頻電路應用於毫米波混頻器，利用fT倍頻電路設計三顆毫米波混頻器。fT倍頻電路即為傳統達靈頓對電路，電路特性即提升fT值，與單顆CMOS電晶體比較可提升近2倍fT值，使受製程限制CMOS電晶體可提升操作頻率，提供足夠電流增益於毫米波頻段。第二部分第一顆電路使用tsmcTM CMOS 0.18 ?m製程，設計“28GHz雙平衡低功耗高增益fT倍頻混頻器”，電路架構利用fT倍頻電路作為轉導級，提升Ka頻段轉換增益，且使用PMOS製作雙平衡吉爾伯特開關級串接轉導級可減少VDD跨壓，降低功率消耗。量測時本振功率-1 dBm時，可得到轉換增益為8.1 dB，輸入功率1-dB壓縮點為-6 dBm，三階交互調變失真點為7 dBm，本地振盪源至射頻與中頻隔離度大於23 dB與44 dB，射頻至中頻隔離度大於33 dB，核心電路功率消耗只需4.95 mW，電路面積0.7 mm2。第二部分第二顆電路使用WIN pHEMT 0.15 ?m製程，設計“60 GHz fT倍頻單平衡混頻器使用集總式威爾金森功率結合器” ，電路架構首先設計威爾金森功率結合器等效模型，利用集總原件完成，相較於傳統使用1/4波長傳輸線威爾金森功率結合器可減少面積。使用集總式威爾金森功率結合器將射頻與本振訊號相加由閘極輸入至fT倍頻電路混頻，利用fT倍頻電路提高V頻段轉換增益，且使用單平衡架構提高各埠隔離度。量測時本振功率1 dBm時，可得到轉換增益為2.2 dB，輸入功率1 dB壓縮點為-6 dBm，三階交互調變失真點為4 dBm，本地振盪源至射頻與中頻隔離度大於13 dB與32 dB，射頻至中頻隔離度大於44 dB，核心電路功率消耗155 mW，電路面積1.5 mm2。第二部分第三顆電路使用UMCTM CMOS 90 nm製程，設計“50 GHz低功耗fT倍頻雙平衡閘極驅動混頻器利用被動結合器技術”，電路架構使用與第一部分相同被動結合器，將射頻與本振訊號相加由閘極輸入至fT倍頻電路混頻。此電路使用四組fT倍頻電路完成雙平衡電路架構，除了提高各埠隔離度以外，更可以利用fT倍頻電路提高V頻段轉換增益。量測時本振功率-2 dBm，可得到轉換增益為-0.76 dB，輸入功率1 dB壓縮點為-7 dBm，三階交互調變失真點為0 dBm，本地振盪源至射頻與中頻隔離度大於29 dB與35 dB，射頻至中頻隔離度大於27 dB，核心電路功率消耗只需2.8 mW，電路面積0.54 mm2。 This thesis develops millimeter mixer circuits. Two kinds of mixers are studied. First, a 60 GHz low power double-balanced gate-pumped (DGP) mixer with passive combiner techniques is designed in tsmcTM CMOS 90 nm process. Using the power combiner and body coupling techniques, the proposed DGP mixer achieves a conversion gain of 3.4 dB, an input 1-dB compression point of - 5 dBm, an input IP3 of 6 dBm at 1-dBm LO power. The LO-RF and LO-IF, and RF-IF isolations are better than 33 dB, 33 dB and 27 dB. The core power consumption is only 0.9 mW and the chip size occupies 0.63 mm2. Second. a fT-doubler topology is adopted to three mm-wave mixer designs. The fT-doubler topology is also called as Darlington pair which improves the fT frequency. Compared with a single CMOS transistor, the fT frequency can arise approximately twice times. Thus, the topology also increases the operating frequency and provides sufficient current gain in millimeter frequencies. The first fT-doubler mixer is a 28 GHz low power high gain double-balanced mixer fabricated in tsmcTM CMOS 0.18 um process. To use the PMOS transistor for the mixer circuit design can reduce the overdrive voltage of the LO switches and the total power consumption. The proposed mixer achieves a conversion gain of 8.1 dB, an input 1-dB compression point of - 6 dBm, an input IP3 of 7 dBm at – 1-dBm LO power. The LO-RF, LO-IF, and RF-IF isolations are better than 23 dB, 44 dB and 33 dB. The core power consumption is only 4.95 mW and the chip size occupies 0.7 mm2. The second fT-doubler mixer is a 60 GHz double-balanced mixer with lumped Wilkinson power combiner fabricated in WINTM pHEMT 0.15 um process. The passive combiner is realized by lumped Wilkinson power combiner which combines the RF with LO signals. Compared with the conventional Wilkinson power combiner, the proposed structure has significant size reduction. Besides, the combined signals are injection into each gate terminal of two coupled fT-doubler topologies to yield the frequency conversion. The fT-doubler topology acts as the transconductance stage of the mixer which not only increases the conversion gain but also improves the port-to-port isolations. The proposed mixer shows a conversion gain of 2.2 dB, an input 1-dB compression point of - 6 dBm, an input IP3 of 4 dBm at 1-dBm LO power. The LO-RF, LO-IF, and RF-IF isolations are better than 13 dB, 32 dB and 44 dB. The core power consumption is 155 mW and the chip size occupies 1.5 mm2. Finally, the third fT-doubler mixer is a 50 GHz low power double-balanced gate-pumped mixer with passive combiner techniques fabricated in UMCTM CMOS 90 nm process. The circuit topology is same as the first one. The input RF and LO signals can be combined by using the passive combiner techniques. Then, the combined signals are injection into each gate terminal of two coupled fT-doubler of the double-balanced mixer to perform the frequency conversion. The proposed mixer obtains a conversion gain of 0 dB, an input 1-dB compression point of - 6 dBm, an input IP3 of 4.3 dBm at 0-dBm LO power. The LO-RF, LO-IF, and RF-IF isolations are better than 29 dB, 35 dB and 27 dB. The core power consumption is only 2.8 mW and the chip size occupies 0.54 mm2.
顯示於類別:	[電機工程研究所] 博碩士論文

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