高功率CMOS微波開關電路設計; Design of High Power CMOS Microwave Switch

NCU Institutional Repository > 資訊電機學院 > 電機工程研究所 > 博碩士論文 > Item 987654321/48529

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题名:	高功率CMOS微波開關電路設計;Design of High Power CMOS Microwave Switch
作者:	王志華;Chih-hua Wang
贡献者:	電機工程研究所
关键词:	高功率;微波開關;High power;RF switch
日期:	2011-08-11
上传时间:	2012-01-05 14:57:15 (UTC+8)
摘要:	由於CMOS製程擁有低成本和高度積體化的優點，因此使數位、類比與射頻電路逐步往系統晶片架構整合發展。然而CMOS的材料及元件例如:低的載子遷移率、低的崩潰電壓和較多的寄生電容特性，使得高頻及高功率相關電路的特性不彰。其中微波開關電路設計受限於不理想的基板效應，而使得功率承受能力降低。為了改善此問題，在本論文中提供了基板偏壓的方法和來改善高功率微波開關特性，並比較不對稱形式(asymmetrical)及行進波式(traveling-wave)的微波開關應用。本論文首先有一導論，主要介紹高功率開關電路的相關研究和發展。接下來會分別介紹三個高功率開關電路。第一個開關電路在發射端子電路中應用了基底開關技術，1.9 GHz操作時此開關電路的發射端可以得到 29 dB的高隔離度。第二個高功率開關電路利用基底接電晶體式的電阻同時將佈局上的寄生效應加入模擬中，最後我們量測到此電路發射端的功率承受能力在1.9 GHz操作下為 28 dBm。第三個高功率開關電路主要為在接收端電晶體的閘極加入並聯的電晶體和使用基底給負偏壓技術，來提高功率承受能力和隔離度，我們量測到此電路發射端的功率承受能力提昇至 34.2 dBm。此外，呈現一個使用雙閘極電晶體的行進波開關電路，我們根據理論和模擬結果證明雙閘極電晶體可以增加開關電路的功率承受能力；此開關的操作頻率為 15 到 70 GHz，量測到此行進波開關電路的0.3-dB壓縮點功率承受能力為 22 dBm，模擬中預測1-dB壓縮點功率承受能力為 24 dBm。 Since the circuit design based on CMOS technology achieves the advantages of low cost and high integration capability. The SoC (system-on-chip) research has being developed with integrating the digital, analog, and RF circuits. However, the material/device characteristics such as low mobility, low breakdown voltage, and large parasitic capacitance always degrade circuit performance for high-frequency and high-power applications. The substrate effect also influences the large-signal characteristic in the microwave switch design, leading to an inferior power handling capability. In order to improve the problem, a method, body/substrate bias, has been proposed in this thesis. The method also was applied to the asymmetrical and the traveling-wave switches. An introduction, illustrating the relative research and development of high power CMOS switch, is presented. Three high-power switch designs for 1.9 GHz operation are following. The first switch demonstrates an isolation of 29 dB in TX sub-circuit with using the body switch technique. A NMOS transistor used to be a resistor at body node is designed and simulated with a layout parasitic effect in the second high-power T/R switch design. The measured power handling capability of TX switch exhibits an input 1-dB compression point of 28 dBm. The third switch incorporates a shunt transistor to the gate of RX transistor and uses the body biasing technique with negative bias. The power handling capability can further be improved to 34.2 dBm at 1.9 GHz. In addition, a traveling-wave switch using a dual-gate transistor is presented. The operating frequency is ranging from 15 to 70 GHz. Based on the theory and the simulation results, the power handling performance can be improved by using dual-gate NMOS transistor in the switch. The measured power handling capability of this traveling-wave switch is about 22 dBm, where it presents 0.3-dB power compression point. The 1-dB power compression point of 24 dBm was also predicted in the simulation.
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