新穎奈米線穿隧式場效電晶體之技術開發; Technology Development of Novel Naonwire Tunneling Field-Effect Transistor

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Title:	新穎奈米線穿隧式場效電晶體之技術開發;Technology Development of Novel Naonwire Tunneling Field-Effect Transistor
Authors:	李明師;Ming-Shih Lee
Contributors:	電機工程研究所
Keywords:	奈米線;PIN;奈米線穿隧式場效電晶體;次臨限斜率;靜態漏電流;Nanowire;PIN;Nanowire Tunneling Field-Effect Transistor;Subthreshold Slope;Static Leakage Current
Date:	2011-08-12
Issue Date:	2012-01-05 14:57:21 (UTC+8)
Abstract:	本論文整合一維複晶矽奈米線與PIN結構於一體，實作出奈米線穿隧式場效電晶體。期望能有效地改善金氧半場效電晶體的短通道效應、次臨限斜率與靜態漏電流。其關鍵製程簡述如下：利用側壁回蝕技術在陡直的平台側壁形成一維複晶矽奈米線，再藉由二次黃光微影製程分別對一維複晶矽奈米線進行P+ 和N+ 離子佈植形成PIN結構，進而實作出奈米線穿隧式場效電晶體。因此於變溫的電流-電壓曲線、次臨限斜率-溫度曲線以及導通電流-溫度曲線進行電性分析。 This thesis integrated one dimension poly-Si nanowire and PIN structure into a device, which fabricated nanowire tunneling field-effect transistor (NWT-FET). We are looking forward to improving short channel effects (SCE), subthreshold slope, (S.S.) and static leakage current (IOFF) in the metal oxide semiconductor field-effect transistor (MOS-FET). The key process of NWT-FET is described as follows: By using etched back technique, we can form one dimension poly-Si nanowire on steep mesa-sidewall. Then by using two photolithography processes, we can implant P+ and N+ on one dimension poly-Si nanowire, respectively, to form the PIN structure. Via the variable temperature measurement (300 K, 250 K, 200 K and 150 K), we experimental characterized the current-voltage (I-V), subthreshold slope-temperature (S.S.-Temp.) and on current-temperature (Ion-Temp.).
Appears in Collections:	[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

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