次微米銻砷化銦鎵基極之異質接面雙極性電晶體製程開發與射極尺寸效應之研究; Development of sub-micron InGaAsSb base double heterojunction bipolar transistors and investigation on emitter size effect

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Title:	次微米銻砷化銦鎵基極之異質接面雙極性電晶體製程開發與射極尺寸效應之研究;Development of sub-micron InGaAsSb base double heterojunction bipolar transistors and investigation on emitter size effect
Authors:	張哲安;Che-An Chang
Contributors:	電機工程研究所
Keywords:	次微米銻砷化銦鎵異質接面雙極性電晶體;射極尺寸效應;sub-micron InGaAsSb base DHBT;emitter size effect
Date:	2011-08-19
Issue Date:	2012-01-05 14:58:32 (UTC+8)
Abstract:	本實驗室先前的研究成果顯示，銻砷化銦鎵基極元件具有低導通電壓、高集極電流密度、高集極電子平均速度、低p型特徵接觸電阻與高電流增益等優點，而為了使元件具有較佳的高頻特性，元件尺寸必須被微縮以降低RC延遲時間。本研究即聚焦於磷化銦HBT之次微米製程技術。我們以電子束微影技術為主的次微米製程，製作射極尺寸為0.8 x 9 um2之砷化銦鎵基極元件，其電流增益截止頻率為290 GHz，相較於射極尺寸1 x 10 um2之元件，上升幅度為46.5 %。此外，在基、集極分別為40 nm與200 nm的試片上，成功將射極尺寸微縮至0.4 x 9 um2，其基-集極電容可降至7.9 fF，且電流增益/最大功率增益截止頻率為272/176 GHz，與射極尺寸1 x 10 um2之元件相比，提升幅度分別為42.4 %與55.8 %。本論文亦說明並解決相較於砷化銦鎵基極元件，次微米銻砷化銦鎵基極元件在製作上所會遇到的困難。此外，為了持續降低元件的RC延遲時間，成功地將射極金屬線寬微縮至0.27 um，並利用混和乾/濕蝕刻製程以同時降低射極與基極電阻，與提出基-集極電容與集極電阻降低之方法。然而在不斷地微縮元件的尺寸時，即會遇到射極尺寸效應，因此本論文亦針對此效應進行研究，提出利用銻砷化銦鎵取代砷化銦鎵基極材料的方式以避免元件尺寸微縮時，造成電流增益的犧牲，並證實銻砷化銦鎵基極元件不需使用複雜的三元或四元複合式射極材料、額外磊晶技術，或射極突出物等製程技術，其射極周圍表面復合電流密度，即可與目前各團隊所發表的最低值相近。此外，當銻砷化銦鎵基極元件之銻含量提升至28 %時，在集極電流密度為0.1 A/cm2下，其射極周圍表面復合電流密度僅為7.37 x 10^-6 uA/um，此值即為各團隊所發表的最低值。因此，本論文之結果皆有助於發展利用銻砷化銦鎵作為元件基極材料，達到THz電晶體之目標。 Recently a new type of heterojunction bipolar transistors (HBTs) with InGaAsSb base was proposed by our group. This novel transistor exhibited low turn-on voltage, high collector current density, high average electron velocity, low specific contact resistivity, and high current gain. In order to elevate the operation frequency of HBTs, the dimension of emitter must be scaled down to the sub-micron level to reduce the parasitic delays. In this work, efforts are focused on developing sub-micron InP-based HBTs. InGaAs/InP HBTs with a 0.8x9 um2 emitter are fabricated by e-beam lithography. The highest current gain cutoff frequency (fT) is 290 GHz, which is superior than the 198 GHz observed on the conventional devices with an emitter of 1x10 um2. Devices with a base thickness of 40 nm and collector thickness of 200 nm exhibit a base-collector capacitance as low as 7.9 fF as the emitter dimension is scaled down to 0.4x9 um2. Meanwhile its fT and power gain cutoff frequency (fMAX) are 272 and 176 GHz, which are 1.424 and 1.558 times higher than those of the 1x10 um2 device, respectively. In the course of this study, many difficulties in fabricating sub-micron InGaAsSb base DHBT are encountered and resolved. Besides, to further reduce parasitic delays, some more processes, such as 0.27 um-emitter metal, hybrid dry/wet etch for emitter, low emitter and base resistance, are developed. As device size is scaled down to deep sub-micron level, surface recombination current increases and device performance degrades. Hence, this work is also involved in the investigation of emitter size effect (ESE). Compared to InGaAs base DHBT, the degradation of current gain is less significant for InGaAsSb base DHBT as device is scaled down. The normalized periphery surface recombination current density (KB,surf) for the InP/InGaAsSb DHBTs fabricated in this work is one of the lowest values among the reported InP-based DHBTs. It means that complicated Emitter/Base junction structures, growth processes and additional device process steps are no longer necessary for the HBTs with an InGaAsSb base. Furthermore, KB,surf as low as 7.37x10^-6 uA/um at Jc = 0.1 A/cm2 has been obtained as the Sb-content in the InGaAsSb base is increased to 28 %. The results obtained in this work provide critical guidelines and routes for achieving THz InGaAsSb base HBTs.
Appears in Collections:	[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

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