本計畫主要探究利用先進鐵電、鐵磁薄膜材料於多晶片模組之電源完整度與電磁干擾防治之實施策略與成效分析。鐵電薄膜材料的高介電常數特性有助於實現超薄與微型化之去耦合電容；鐵磁薄膜材料的高導磁係數則可用於實現抗電磁干擾濾波器；鐵電與鐵磁薄膜的搭配設計，則有機會於多晶片模組實現高度整合之電源完整性與電磁干擾防治解決方案。相較於過去文獻與研究計畫多集中探討於多晶片模組封裝基板實現內埋式被動電路設計，進而搭配主動電路晶片，實現高整合度的微型化收發模組，本計畫將進一步開發鐵性薄膜材料於多晶片模組封裝基板之應用，如此一來，除微波主、被動電路之外，尚可進一步於模組中整合電源完整性與電磁干擾解決方案，實現「完整」的單一系統封裝模組架構，對於微波與毫米波單一系統封裝技術發展而言可謂大幅向前邁進一步。 The purpose of this study is to investigate the application of ferroelectric and ferrite thin-films to the power integrity and electromagnetic interference (EMI) reduction of multi-chip modules. Ferroelectric thin-film exhibits high dielectric constant, and can be used to implement miniature and ultra-thin de-coupling capacitor. Ferrite thin-film possesses high permeability, and can be applied to the design of miniature EMI filters. A proper combination of ferroelectric and ferrite thin-films has the potential to realize highly integrated power integrity and EMI solutions for multi-chip module applications. Compared to the conventional designs of multi-chip modules that focus on the implementation of embedded passives in the module substrate and connect the active circuit chips through wire-bonding or flip-chip, the proposed technology introduce the possibility to also integrate power integrity and EMI solutions in the module substrate throught the use of advanced ferroelectric and ferrite thin-film processes. In this way, a complete “system-on-package” archtecture can be delievered, and it represents a major leap forward in terms of the level of integration for system-in-a-package technologies. 研究期間：10008 ~ 10107
