A 5.5-GHz 1-mW Full-Modulus-Range Programmable Frequency Divider in 90-nm CMOS Process

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題名:	A 5.5-GHz 1-mW Full-Modulus-Range Programmable Frequency Divider in 90-nm CMOS Process
作者:	Lin,CS;Chien,TH;Wey,CL
貢獻者:	電機工程學系
關鍵詞:	SYNTHESIZER;NOISE
日期:	2011
上傳時間:	2012-03-28 10:13:17 (UTC+8)
出版者:	國立中央大學
摘要:	Operating up to 5.5 GHz with 1-mW power consumption, a 90-nm CMOS programmable frequency divider with eight stages of new static D-flip-flop-based (2/1) divider cells is presented, where the supply voltage of 1.0 V is employed. The divider achieves a full modulus range from 1 to 256 and operates over a wide range maintaining up to 4 GHz with -30-dBm input power. The divider also accomplishes a power efficiency of 12.8 GHz/mW with 0.5-V supply voltage. It is favorable for advanced processes.
關聯:	IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
顯示於類別:	[電機工程學系] 期刊論文

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