高效率物件切割硬體加速器設計與立體視覺應用;Design and Implementation of a High-Efficiency Segmentation Hardware Accelerator and Application in Stereo Vision

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题名:	高效率物件切割硬體加速器設計與立體視覺應用;Design and Implementation of a High-Efficiency Segmentation Hardware Accelerator and Application in Stereo Vision
作者:	黃彥翔;Huang,Yen-hsiang
贡献者:	資訊工程研究所
关键词:	SOM神經網路;立體視覺;物件切割;FPGA;stereo vision;segmentation;FPGA;SOM neural network
日期:	2012-07-04
上传时间:	2012-09-11 18:49:40 (UTC+8)
出版者:	國立中央大學
摘要:	典型的立體視覺原理是基於雙攝影機同步取像和一系列複雜的影像處理，在軟體開發通常需要高效能的處理器以實現複雜演算法，因此使得立體視覺在即時與嵌入式系統的實現開發上受到成本與即時性技術上的限制。本研究藉由MIAT嵌入式硬體設計方法論，設計一個基於SOM神經網路的高效率物件切割硬體加速器，對影像進行色彩切割，並將物件連通標定與基於SAD的立體匹配演算法設計成硬體電路，再以管線化控制器進行平行化架構整合，進而合成全硬體的高速立體視覺系統。其性能可達13.8 Frames/sec，可滿足即時系統需求。其中的高效率物件切割硬體加速器，大幅減少物件切割模組的記憶體存取次數，有效提升物件切割效能。A typical stereo vision principle basically consists of two parts. One is the image extracted using two synchronous cameras, and another is a series of complex image processing. However, high-efficacy processors are often required to implement complex algorithms in software development. Thus, stereo vision is difficult to be achieved on the embedded system applications, because of its low-cost and limited resources. In this paper, we designed a high-efficiency segmentation hardware accelerator, based on SOM (Self-Organizing Map) neural network and using Hierarchical Robotic Discrete-Event Modeling, for color segmentation. Then, all the algorithms, connecting component labeling and stereo matching using SAD (Sum of Absolute Difference), were implemented as hardware and integrated with a pipeline controller. Finally, we synthesize a high-speed stereo vision as hardware system. As a result, our system is able to generate images at the speed of up to 13.8 images / sec. This performance makes our system usable in real-time embedded systems. Above all, we reduce the memory access times significantly and raise the performance effectively in high-efficiency segmentation hardware accelerator.
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