使用可調式負載及面積縮放技巧提升功率放大器之效率;Power Amplifier Efficiency Enhancement Using Tunable Load and Area Resizing Techniques

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Title:	使用可調式負載及面積縮放技巧提升功率放大器之效率;Power Amplifier Efficiency Enhancement Using Tunable Load and Area Resizing Techniques
Authors:	王珮暻;Wang,Pei-ching
Contributors:	電機工程研究所
Keywords:	功率放大器;可調式負載;Power Amplifier;Tunable Load
Date:	2012-07-23
Issue Date:	2012-09-11 18:53:04 (UTC+8)
Publisher:	國立中央大學
Abstract:	功率放大器是射頻前端功率消耗最多的單一電路元件，因此提升其將直流功率轉換為射頻功率的效率對系統整體功耗的降低有長足影響。本論文將討論可調式負載及面積縮放這兩個效率改善技巧，並將之用於CMOS功率放大器設計實際驗證之。我們設計了兩個操作於2.535 GHz使用可調式負載及面積縮收技巧的功率放大器，皆使用TSMC 0.18-μm CMOS製程實現。第一個放大器具有兩路面積切換及兩種負載阻抗切換；在3.3 V供應電壓下，此功率放大器之P1dB為23.1 dBm，相對應之PAE為31.2%。使用面積縮放及負載切換，在大於3-dB功率回退的情況下，直流功耗可降低40%以上。第二個放大器具有八路面積切換及兩種負載阻抗切換，並包含一適用於多路面積切換的旁路電容共用設計；在3.3 V供應電壓下，模擬之P1dB為21.2 dBm，相對應之PAE為30.6%；在3-dB功率回退的情況下，可使直流功耗降低40%。我們成功地驗證結合面積縮放及可調式負載技巧可有效降低功率放大器於低功率區的直流功率消耗，並大幅提升其效率。A power amplifier (PA) is the most power-hungry circuit block in a RF frontend. Increasing its efficiency of transferring the DC power to RF power is therefore eminent when it comes to reducing the DC power consumption of RF systems. This thesis discusses two efficiency-enhancing techniques, namely, tunable load and area resizing. The techniques are applied to and verified by two CMOS PA designs.Based on tunable-load and area-resizing techniques, two switchable PAs operating at 2.535 GHz are designed and implemented in TSMC 0.18-μm CMOS technology. The first PA can be switched between two states; each state has a different transistor size and corresponds to a different load impedance. At 3.3-V supply voltage, the P1dB and the corresponding PAE are 23.1 dBm and 31.2%, respectively. By resizing the area and switching the load impedance, the DC power consumption of the PA can be reduced by more than 40% as the power is backed off by 3 dB or more. The second PA has 8 area-resizing states and its load impedance can be switched between two different values. In addition, it contains a bypass-capacitor-sharing design that suits area-resizing with multiple controls. Simulation results show, at 3.3-V supply, the P1dB and the corresponding PAE are 21.2 dBm and 30.6%, respectively. The DC power consumption is reduced by 40% at 3-dB power back-off.It is successfully demonstrated that, combining area resizing and tunable load techniques, the DC power consumption of PAs at low-power region can be effectively reduced and the power efficiency can be significantly enhanced.
Appears in Collections:	[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

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