應用於電容陣列區塊之維持良率的二冪次分割及權重優先序擺置法; 2CWP-CABC: A Yield-aware Placement with Power-of-Two Cutting and Weighted Priority for the Capacitor Array Block Creator

NCUIR > College of Electrical Engineering & Computer Science > Graduate Institute of Electrical Engineering > Electronic Thesis & Dissertation > Item 987654321/61141

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Title:	應用於電容陣列區塊之維持良率的二冪次分割及權重優先序擺置法;2CWP-CABC: A Yield-aware Placement with Power-of-Two Cutting and Weighted Priority for the Capacitor Array Block Creator
Authors:	王瑜薪;Wang,Yu-Hsin
Contributors:	電機工程學系
Keywords:	電容陣列;電容陣列
Date:	2013-07-22
Issue Date:	2013-08-22 12:13:05 (UTC+8)
Publisher:	國立中央大學
Abstract:	隨著半導體製程技術的進步，從0.18um、90nm到現今最小可到22nm，製程變動(process variation)所造成元件之間的不匹配(mismatch)越來越嚴重，這代表著類比電路設計上的複雜度與時間成本越來越高，佈局的自動化設計便成為電路設計過程中一個關鍵的角色。在現今多數的類比數位電路之中，像是類比數位/數位類比轉換器或濾波器等等，其性能都取決於準確的電容比值。所以，如何達到準確的電容比值就成為一個很重要的議題。為了達到精確的電容比值，設計上會以並聯多顆較小的單位電容來取代一顆大電容，並利用空間相關性來解決製程上變動所帶來的問題。其中，要切割成多少顆單位電容及如何擺放在電容陣列就成為佈局擺置自動化中非常重要的一環。本論文提出一種應用於電容陣列區塊佈局之維持良率的二冪次分割及權重優先序擺置法電容陣列佈局的方法。我們透過改變元件擺放的優先順序，依照不同的電路限制去改變權重的優先順序，將擺放出較佳的排列。並且我們建立一個二冪次的矩陣架構，並提出了一種二冪次電容切割法，運用此方法在電容擺置上就能達到高分散性(dispersion)、耗時少且精確度高的電容陣列佈局。最後舉出幾個不同的排列方式，藉由不同電容陣列的擺放結果來說明擺放對於陣列的影響。最後針對特定電路的特定電容組成的陣列進行比較。佈局完成後再透過Monte Carlo方法進行驗證，結果顯示電容比的匹配度提高且電路的良率提升。 As the evolution of semiconductor process technology from 0.18um, 90nm to the present minimum is 22nm, the process variation will be more and more serious in device mismatch. This represents the analog circuit design increase time-consuming and high complex, then layout automation is likely to play a key role in analog circuit design. The performance of many types of analog circuits, like ADC, DAC, filter, etc., relies on the implementation of accurate capacitor array ratios. In order to reduce the negative effects, designers are determined by properly arranging the identical unit-size capacitors and used spatial correlation to decrease the effect of process variation. Among them, how many unit-size capacitor you want to cut and how to assign the capacitance in capacitor array has become a very important part with automatic layout assignment. In this thesis, we propose a layout assign method a yield-aware placement with power-of-two cutting and weighted priority for capacitor array block creator. We place by changing the priority of capacitor according to different circuit constraints, the placement will be place in a better result. And we have established a power-of-two matrix structure, and propose a power-of-two capacitance cutting method. Used this method in the capacitor placement can achieve high dispersion, less time-consuming and the accuracy of capacitor array layout. Finally, we cite a few different placements to illustrate the impact of placing the array. For a particular circuit, various assignment capacitor arrays are validated by their circuit yield, which is done by Monte Carlo method. The results show the matching of capacitor ratio increased and the circuit yield enhancement.
Appears in Collections:	[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

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