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    Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/61850

    Title: 應用於電容陣列區塊之維持良率的皇后比例切割法;QRC-CABC: A Yield-aware Placement with Queen Ratio Cutting for the Capacitor Array Block Creator
    Authors: 黃志偉;Huang,Chei-Wei
    Contributors: 電機工程學系
    Keywords: 電容陣列;電容擺放;capacitor array;capacitor placement
    Date: 2013-11-28
    Issue Date: 2014-02-13 17:52:40 (UTC+8)
    Publisher: 國立中央大學
    Abstract: 近年來,隨著半導體製程技術的進步,製程變動(process variation)所造成元件之間的?匹配(mismatch)越來越嚴重,這代表類比電路設計上的複雜度與時間成本越來越高,佈局的自動化設計便成為電路設計過程中的關鍵角色。在現今多?的類比?位電路之中,像是類比?位/?位類比轉換器或?波器等等,其性能?取決於準確的電容比值。所以,如何達到準確的電容比值就成為一個很重要的議題。而為了達到精確的電容比值,設計上會以並聯多顆較小的單位電容來取代一顆大電容,並利用空間相關性來解決製程變動所帶來的問題。其中,要切割成多少顆單位電容及如何擺放在電容陣列就成為佈局擺置自動化中非常重要的一環。 本論文提出一種應用於電容陣列區塊佈局之維持良率的皇后比例切割法的電容陣列佈局方法。我們將電容分成三大類來進行擺放,其一為直接擺放的皇后電容,其二為優先考慮最後擺放的貼身婢女電容,其三為最後考慮優先擺放的孚護騎士電容。此外,還特別制定了一個燈塔孚護機制,用來加入適當的空乏電容完成擺放。運用此方法在電容擺置上就能達到高分散性(dispersion)、耗時少且精確度高的電容陣列佈局。最後針對特定電路的特定電容組成的陣列進行比較。佈局完成後再透過Monte Carlo方法進行驗證,結果顯示電容比的匹配度提高且電路的良率提升。
    As the advancement of semiconductor process technology, the process variation will be more and more serious in device mismatch for the analog integrated circuits. There are several placement algorithms presented to improve the capacitance ratio matching due to spatial correlation. In this thesis, a new yield-aware placement, named queen ratio cutting (QRC), is proposed for the capacitor array block creator (CABC). In QRC, there are four types of target capacitors to be assigned the position: queens, servant-girls, protection knights and Rooks. Queens are directly placed according to the rule of N-Queens Problem. Servant-girls are preferential considered and last placed. Protection knights are last considered and preferential placed. Rook assignment is to solve the dummy remainders in capacitor array. QRC is implemented and integrated in CABC. Several different continuous ratios are used as benchmarks to test the performance. It is shown that QRC reaches the better ratio yield with less area, where each ratio must be within 3-percent deviation.
    Appears in Collections:[電機工程研究所] 博碩士論文

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