注入鎖定除頻器之研究及其鎖相迴路應用; Research on Injection-Locked Frequency Divider and Its Phase-Locked Loop Application

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Title:	注入鎖定除頻器之研究及其鎖相迴路應用;Research on Injection-Locked Frequency Divider and Its Phase-Locked Loop Application
Authors:	林宗憲;Lin,Tsung-Hsien
Contributors:	電機工程學系
Keywords:	鎖相迴路;注入鎖定;頻率除頻器;除六;振盪器;Phase-locked loop;injection-locked;frequency divider;divide-by-6;oscillator
Date:	2013-12-23
Issue Date:	2014-02-13 17:53:01 (UTC+8)
Publisher:	國立中央大學
Abstract:	本論文主要針對應用於微波與毫米波鎖相迴路之注入鎖定技術。第二章與第三章分別闡述應用於鎖相迴路中的注入鎖定除頻器及其鎖相迴路應用。第四章為注入鎖定振盪器的電路設計與量測結果。第二章介紹各類除頻器架構以及設計原理，並且提出注入鎖定除六與除五除頻器對鎖定頻寬的理論模型，從理論模型分析得知，鎖定頻寬跟注入器(injector)的元件與注入訊號大小成正比。同時採用台積電提供的90 nm低功耗互補式金氧半場效電晶體製程(TSMC 90 nm LP CMOS)實現注入鎖定除六除頻器，量測最大鎖定頻寬為2.9 GHz。第三章是將第二章所提出之除六除頻器整合至鎖相迴路系統，並且討論外在環境對量測電路的影響，提出實質的解決方案。同樣是使用台積電提供的90 nm製程實現，鎖相迴路的鎖定頻寬為25.3~27.3GHz，輸出功率接大於-8 dBm。在鎖定頻率為25.38 GHz，在距離中心頻10 kHz、100 kHz與1 MHz下，分別為-86.4、-90.7與-91.69 dBc/Hz。電路直流總功耗為40 mW，達到低直流功耗的效果。第四章提出一個使用基級注入鎖定振盪器。藉由調整閘極端的電壓與基級注入鎖定技術，改善輸出相位雜訊與鎖定頻寬。使用台積電提供的90 nm製程實現，在振盪頻率為50 GHz、60 GHz與70 GHz下，有最寬的鎖定頻寬百分比分別為7.8%、13.8%與14.7%，總直流功耗為31.2~44.4mW。 This thesis focuses on the injection-locked technique for the microwave and millimeter-wave phase-locked loop (PLL). A Ka-band injection-locked frequency divider (ILFD) and its PLL application are presented in Chapter 2 and 3, respectively. Finally, The design and analysis results of a V-band injection-locked oscillator (ILO) are proposed in Chapter 4. Several frequency dividers and the injection-locked theory are introduced in Chapter 2. The locking range of divide-by-6 and divide-by-5 ILFDs is investigated to obtain the design methodology. From the analysis, the locking range of ILFDs is proportional to the device size of the injectiors and the amplitude of the injection signal. The proposed divide-by-6 ILFD is fabricated using TSMC 90 nm low power (LP) CMOS process and it features with a locking range of 2.9 GHz. Moreover, the proposed divide-by-6 ILFD is applied to a fully integrated Ka-band PLL. Several DC bypass networks for the measurement is discussed to further reduce the baseband /DC noise, and the effective solution is also addressed. The measured output phase is -86.4, -90.7, and -91.69 dBc/Hz at 10 kHz, 100 kHz, and 1 MHz offset at 25.38 GHz. The total DC consumption of PLL is about 40 mW. The proposed injection-locked oscillator using TSMC 90 nm LP CMOS process is presented in Chapter 4. With the body-injection technique, wider locking range can be achieved. As the oscillation frequency are 50, 60, and 70 GHz, the widest locking ranges percentage at 7.8%, 13.8% and 14.7%, respectively. The total DC power consumption is about 31.2~44.4 mW.
Appears in Collections:	[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

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