| 摘要: | 研究期間：10308~10407;This project proposes the research and development of a multi-phase high performance signal source for K-band phase array radar applications. The signal source will be designed using CMOS process. The signal source has 16-phase outputs with a phase resolution of 22.5∘, a frequency stability of within 5 ppm, a phase noise of -100 dBc/Hz at 1-MHz offset, a settling time of within 300 μs, and an RF power of 0 dBm for signal output. The overall dc power consumption is within 1 W. In order to improve the phase noise of the signal source, an injection-locked technique will be employed. The output phase noise will be -120 ~ -130 dBc/Hz @ 1-MHz offset, and the phase nosie will be improved by 10 to 20 dB with the same dc power consumption. The research topics contain the development of the injection-locked phase-locked loop (ILPLL) theoretical model, analog, digital integrated circuits, and package technology. The integrated circuit components will include injection-locked multi-phase voltage-controlled oscillator, frequency divider, programming counter, digital-controlled interface circuit, phase detector, charge pumping, filter and switch. The project will be carried out following the below procedures: 1) design and simulation the ILPLL source, 2) establish the design goals of sub-circuit systems, 3) survey the related integrated circuit foundries and the device modeling, 4) establish the passive components and digital logic cell libraries, 5) implement and fabricate the single-circuit chips, 6) measure and verify the chips, 7) develop the source module, 8) integrate the sub-circuit into a single chip, and 9) investigate the experimental results. In this project, the establishment of the ILPLL integrated circuit (IC) technology, the innovative low noise ICs, the related high speed measurement technology, and the system-on-chip signal source will be achieved. Also, we will train the project participants to gain the high speed system and IC related experiences. The system planning, IC design, chip layout, fabrication and chip evaluation will be exercised. The design and layout will also be completed and sent to foundry for fabrication. Final, the measurement and analysis of the developed ICs will be presented. |
