應用於三維積體電路可測性及可靠性設計技術---總計畫暨子計畫一：三維積體電路中堆疊式記憶體與晶粒間連接線可測性與可靠性技術;Design-for-Testability and Reliability Techniques for Stacked Rams and Inter-Die Interconnection in 3D ICs

NCUIR > College of Electrical Engineering & Computer Science > Department of Electrical Engineering > Research Project > Item 987654321/67881

Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/67881

Title:	應用於三維積體電路可測性及可靠性設計技術---總計畫暨子計畫一：三維積體電路中堆疊式記憶體與晶粒間連接線可測性與可靠性技術;Design-for-Testability and Reliability Techniques for Stacked Rams and Inter-Die Interconnection in 3D ICs
Authors:	李進福
Contributors:	國立中央大學電機工程學系
Keywords:	電子電機工程
Date:	2015-09-11
Issue Date:	2015-09-11 15:27:39 (UTC+8)
Publisher:	科技部
Abstract:	研究期間：10405~10504
Relation:	財團法人國家實驗研究院科技政策研究與資訊中心
Appears in Collections:	[Department of Electrical Engineering] Research Project

Files in This Item:

File	Description	Size	Format
index.html		0Kb	HTML	337	View/Open

社群 sharing