隨著超大型積體電路的快速演進，電路的可繞度（Routability）問題愈趨嚴重。一般在繞線階段時才能準確得知電路可繞度之資訊，然而若此時才發現電路的可繞度不足，在設計上會浪費大量的時間重新進行擺置與再繞線。因此若在擺置階段就考慮電路的可繞度資訊並能及時發現問題，即可避免時間的浪費。 為了精準的預估可繞度，本篇論文採用全域繞線研究做為基底，但目前絕大部分的全域繞線研究皆沒有考慮細部繞線階段可能產生的壅塞問題，這導致即使完成了全域繞線，仍有相當大的機率無法得到無壅塞（Congestion-free）的細部繞線結果。因此，本篇論文提出了適用於擺置階段的快速區域壅塞模型（Local congestion model），搭配適合在擺置階段使用的快速全域繞線器，能夠提早預知區域壅塞的情形，並且提早迴避壅塞區域（Congested region），或者識別不可繞（Unroutable）的電路。實驗結果顯示，本篇論文所提出的方法可以在短時間內預估電路的區域壅塞，使得全域繞線器可以提早得知細部繞線階段之可繞度資訊。 ;With the advances of Very-Large-Scale Integration circuits, the routability problem has become more and more significant. Conventionally, circuit routability can only be evaluated precisely after routing stage. However, if the routability is not sufficient, it will waste lots of time to re-place and re-route. Thus, routability evaluating in placement stage is important to discover potential routing problems and avoid redesign efforts. For accurate routability evaluation, this thesis proposes a method based on global routing. However, most of the global routing researches didn’t consider the possible congestions occurred in the detailed routing stage. It is possible that congestion-free detailed routing results are still not available. Therefore, a fast local congestion model for placement stage is proposed in this thesis. Combined with a fast global router, the proposed fast local congestion model can predict the distribution of routing congestion to avoid congested regions and identify unroutable circuits. Experimental results showed that the proposed model can obtain local congestion information fast in placement stage and help the global router to evaluate the routability of the circuits.
