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    請使用永久網址來引用或連結此文件: http://ir.lib.ncu.edu.tw/handle/987654321/72072


    題名: 串聯及並聯陣列結構對準單模 850 nm光波段垂直共振腔面射型雷射之調制速度和輸出功率表現的增強;Series and parallel quasi-single-mode 850 nm Vertical-Cavity Surface-Emitting Lasers Array with Enhanced Speed and Output Power Performances
    作者: 陳信男;Chen,Xin-Nan
    貢獻者: 電機工程學系
    關鍵詞: 半導體雷射;垂直共振腔面射型雷射;光連結;Semiconductor lasers;Vertical cavity surface emitting lasers;Optical Interconnect
    日期: 2016-06-20
    上傳時間: 2016-10-13 14:24:37 (UTC+8)
    出版者: 國立中央大學
    摘要: 在我們的實驗中,展現了串聯及並聯高速垂直共振腔面射型雷射(VCSELs)陣列的操作,兩個結構相比於單顆操作的元件,都顯示出在輸出功率的提升,及其在最大調製速度(electrical-optical (E-O) bandwidth)上並沒有任何的退化,能夠得到速度沒有劣化的結果,最主要源自於我們特殊的氧化掏離(oxide-relief)技術,以及鋅擴散技術(Zn-diffusion),大大的釋放了RC限制的頻寬(RC-limited),有效降低微分電阻(differential resistance)及寄生電容( parasitic capacitance)。另外,把陣列中的VCSEL經由高密度排列,因其具有鋅擴散孔徑用於光的模態抑制(optical mode control),此結果可以大大降低輸出能量從我們的陣列結構耦合到標準的多模光纖(MMF)的損耗(coupling loss)。
    相較於我們一般單顆的元件,並聯陣列結構在傳輸性能上有顯著的增強,並聯結構有著較大的眼緣(eye margin),較高的信噪比(signal-to-noise ratio),及擁有較高的數據傳輸量(44v.s.50Gbit/s)。根據我們的結構模擬技術,並聯陣列的增強是由於其內部阻抗(internal resistance)更接近於信號源的50Ω,另一方面,串聯的傳輸效能與之相比明顯的降低,這是由於其內部阻抗增加,使其元件與設備間的阻抗匹配也跟著增加的問題。;Parallel and series high-speed VCSEL array have been demonstrated in this work. Both structures show improvement in output power and have no degradation in its maximum modulation speed as compared to those of single reference. The observed invariant electrical-optical (E-O) bandwidth in our parallel and series array is mainly due to the wide RC-limited bandwidth of unit VCSEL with Zn-diffusion and oxide-relief aperture for reducing differential resistance and parasitic capacitance, respectively. Furthermore, by densely packing the single unit VCSEL, which has Zn-diffusion apertures for optical mode control, the increasing in coupling loss between the outputs from our array into a standard MMF can be minimized. Compared with reference unit VCSEL, the parallel VCSEL array shows a significant enhancement in transmission performance over 100 meter OM4 fiber, which includes a larger eye margin, a higher signal-to-noise ratio, and at a higher data rate (50 vs.44 Gbit/sec). By performing device modeling technique onto our devices, we can conclude that such improvement of parallel array is because that it has a value of internal resistance more close to the 50Ω signal source. On the other hand, the transmission performance of series array degrades significantly as compared to that of single reference due to the increase in its internal resistance and more serious impedance mismatch between device and signal source.
    顯示於類別:[電機工程研究所] 博碩士論文

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