| 摘要: | 摘要 本論文中主要是探討與研究表面絕緣層在氮化鎵或氧化鋅系列寬能隙半導體材料上的應用，數個表面絕緣層在氮化鎵金半金光偵測器、異質結構場效電晶體或氧化鋅場效電晶體上的研究與應用分述如下： 具有低溫成長氮化鎵表面絕緣層結構的氮化鎵金屬-半導體-金屬光偵測器由於電極具有較高的蕭特基能障，被發現可以降低暗電流達兩個數量級，進而令紫外光對可見光的光感應電流比例由10 倍增加至2000 倍左右，大大的提升其對紫外光的偵測鑑別度與降低誤差值。當元件偏電壓在1 與5 伏特的時候，此具低溫成長氮化鎵表面絕緣層氮化鎵金半金光偵測器的光響應度分別可達0.13 與3.3 安培/瓦。 另外以低溫成長氮化鎵、二氧化矽或四氮化三矽為表面絕緣層的氮化鋁鎵/氮化鎵異質結構場效電晶體也在本論文中被研究。上述的表面絕緣層有可能改變了氮化鋁鎵/氮化鎵異質結構場效電晶體的表面能態與材料的應力結構，進而影響了材料中的載子捕捉與偏極化作用，結果提升了材料中的載子濃度與場效電晶體元件的飽和電流。經由霍爾量測可以發現，與不具有表面絕緣層的結構樣品相比，具有表面絕緣層結構的樣品載子濃度提升約為百分之五十。此項結果是可以逆轉的，若將具有低溫成長氮化鎵表面絕緣層樣品表面的低溫成長氮化鎵用活性離子蝕刻機移除，其載子濃度即會有顯著的下降。此外由於低溫成長氮化鎵的成長特性，使其具有高晶格常數匹配與低表面污染的優勢，讓具有低溫成長氮化鎵表面絕緣層的氮化鋁鎵/氮化鎵異質結構場效電晶體不論在直流、脈衝還是高頻量測上都有較為傑出的表現。 最後氧化鋅金屬-半導體場效電晶體與金屬-氧化物-半導體場效電晶體元件也被製作並比較。由這次的研究指出，氧化鋅金屬-半導體場效電晶體閘極電流過大，使得其元件操作特性與能力受到很大的影響。具有氧化層的氧化鋅金屬-氧化物-半導體場效電晶體則展現低一個數量級的閘極漏電流，並具有較好的元件操作特性。另外使用玻璃與藍寶石基板的樣品在這裡也被比較，不論使用哪一種基板，成長厚的氧化鋅緩衝層是必要的。0.8~0.9 微米厚的氧化鋅緩衝層可以成長出較高品質的氧化鋅主動層並且有效降低閘極漏電流與元件-元件間的絕緣漏電流。 最後總結說來，表面絕緣層可以提升蕭特基能障、降低蕭特基電極漏電流、減少表面能態進而穩定並增進元件特性。吾人可藉由表面絕緣層這樣的特性，研究並開發出低成本並且高品質的元件。 Abstracts In this dissertation, the applications of insulators/oxides on GaN-based MSM photodectors or GaN-, ZnO-based FETs are performed. Several application cases and theories of insulator on GaN- and ZnO-based devices are introduced here: GaN-based MSM UV photodetectors with a low-temperature grown GaN (LT-GaN) layer is demonstrated first. It was found that we could achieve a two-order of magnitude smaller, dark-current of GaN MSM photodetector by employing a LT-GaN surface insulating layer. This result could be attributed to the larger Schottky-barrier height between the Ni/Au metal contact and the LT-GaN surface insulating layer. It was also found that photodetectors with the LT-GaN layer could provide a larger photocurrent to dark-current contrast ratio and a larger UV-to-visible rejection ratio. The maximum responsivity was found to be 3.3 A/W and 0.13 A/W when the biases were at 5 V and 1 V, respectively. The performance of AlGaN/GaN heterostructure field-effect transistors (HFETs) with either uncapped free surface or with LT-GaN, SiO2, Si3N4 as gate insulators is examined second. LT-GaN, SiO2 and Si3N4 surface high-resistivity layer disposed on the AlGaN/GaN heterostructures resulted in an increase of sheet carrier concentrations. These observations could be attributed from the passivation effect to passivate the surface states, thereby having a different, maybe lower, electronic density of states compared to the AlGaN free surface. To clarify the effect of these surface insulating layers on the AlGaN/GaN HFET structures, Hall measurement were performed here. The sheet carrier concentrations of AlGaN/GaN HFETs with any of these surface insulating layers are similar to each other and about 100% higher than that in an AlGaN/GaN HFET structure with a free surface. Due to the better lattice match with the AlGaN surface layer, the HFET with a LT-GaN layer as the gate insulating layer shows the best DC and RF device performance, demonstrating that this material is an effective insulator for nitrides. Comparison of ZnO MOSFETs and MESFETs fabricated on the same wafers using either sapphire or glass substrate is report finally. ZnO thin film field effect transistors with 1.5-20um gate width were fabricated using either a metal gate (metal-semiconductor field-effect transistor, MESFET) or a metal-oxide-semiconductor (MOS) gate. In both cases we found that use of a thick (around 0.8~0.9µm) ZnO buffer was necessary on the sapphire or glass substrate prior to growing the active layers in order to reduce gate leakage current. The MOS structure with a 50-nm-(Ce,Tb)MgAl11O19 gate dielectric showed an order of magnitude lower gate leakage current than the MESFET, due to the relatively high barrier height of MOS structure. Good drain-source current characteristics were obtained from MOS gate structures using phosphorus-doped ZnO channels, whereas the metal structures showed very poor modulation. For the general speaking form this dissertation, surface insulating layer could provide device high Schottky barrier height, low metal/semiconductor leakage current, low surface state density and highly stable device performance. One may use surface insulating layer to achieve more stable, even higher, performance of semiconductor device easily. |
