本論文研究內容以軟體定義無線電實現DVB-S2發射端，包含BCH碼，LDPC碼，Bit interleaver和調變器。本論文將現有的DVB-S2規格書加以整合實現，並以FPGA(AC701)和AD9361作realtime呈現。在實現設計中因為硬體最高速度的限制下，實現real time需加以計算每個碼率的throughput 和 symbol rate，經過所有 code rate的throughput 和 symbol rate計算後 ，決定將LDPC編碼採平行輸入編碼，此方式可減少倍數的編碼時間使throughput 能夠提升。而整合系統的部分，因為兩種編碼的碼率多樣性，使得為了節省硬體資源必須將編碼器以良好的參數設計方式設計，並且要考量架構種類以便硬體上的實現。本論文所整合的發射機可藉由簡易的參數入控制所需要發射訊號以實現高資料量的DVB-S2發射機。 ;The second generation digital satellite broadcasting (DVB-S2) is a new generation of digital satellite broadcasting standards to enhance the transmission relative to DVB-S. In the channel coding, the LDPC code is used as the inner code, the BCH code is used as the outer code, and the two error correction codes are combined to provide good error correction capability, and the LDPC code has two code lengths, as well as various code rates, Different needs.
In this thesis,we design and implementation of DVB-S2 Transmitter with SDR Platform,including BCH code, LDPC code, Bit interleaver and modulator. This paper is based on the existing DVB-S2 specification to be integrated, and the laboratory supply of FPGA and AD9361 for realtime presentation.In order to achieve real time we must calculate the throughput rate of each code rate and symbol rate, after all the code rate throughput and symbol rate calculation, this paper decided to LDPC encoding parallel input coding, this method can reduce the multiples of the encoding time to make Throughput can be improved. The integrated transmitter of this thesis can be used to control the signal transmission by simple parameters to achieve high-volume DVB-S2 transmitter.
