基於磁耦合全通網路與鐵電可變電容之類比式相位偏移器;Analog Phase Shifters Based on Magnetically Coupled All-Pass Networks and Ferroelectric Varactors

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Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/73031

Title:	基於磁耦合全通網路與鐵電可變電容之類比式相位偏移器;Analog Phase Shifters Based on Magnetically Coupled All-Pass Networks and Ferroelectric Varactors
Authors:	黃皓芃;Huang, Hao-Peng
Contributors:	電機工程學系
Keywords:	Phase shifter;Ferroelectric varactors;All-pass networks
Date:	2017-01-24
Issue Date:	2017-05-05 17:39:31 (UTC+8)
Publisher:	國立中央大學
Abstract:	以具磁耦合的全通網路來實現相位偏移器時，兩耦合電感間的耦合係數k值若小於零可增加相位偏移響應的頻寬，而k若為大於零則可提升相位偏移量。本論文使用k > 0的磁耦合全通網路與鐵電可變電容來實現兩個高相移量的類比式相位偏移器。根據耦合電感佈局是否對稱，此二相移器分別稱為：非對稱型相移器與對稱型相移器。兩相移器皆使用我們所開發的積體被動元件製程來製作。其中，非對稱型相位偏移器設計操作於10 GHz，製作於藍寶石基板上。量測結果顯示，當鐵電可變電容偏壓由0 V調至6 V時，相移量在8.5 GHz達到最大值，為67.3°。從dc至12 GHz，植入損耗皆小於4.5 dB，返回損耗皆大於10 dB。相移量最大值的頻率由原始設計之10 GHz偏移至8.5 GHz是由於實際製作出的電容值大於設計值。另外，我們發展了具矽基板貫孔的鐵電可變電容的製程，並應用於對稱型相位偏移器之設計。此相移器設計於2.45 GHz，預期可達到約60°的相移量；然而，量測結果顯示此相移器並未呈現全通之響應。經檢視電路照片，我們發現在金電鍍後，兩耦合電感間出現不在預期中的金屬連接。將此連接加入模擬後，發現和量測結果相當吻合，驗證此為造成量測結果與原始模擬結果有相當大差異的原因。本論文成功設計並製作非對稱型相位偏移器，展示以k > 0的磁耦合全通網路用於實現類比式相位偏移器之潛力。而對於對稱型相位偏移器，我們也確認失敗是由於製作上的失誤所造成。 ;When using magnetically coupled all-pass networks (MCAPNs) to realize phase shifters, the bandwidth over which the phase shift remains constant can be increased if the coupling coefficient, k, between the two inductors are designed to be negative, whereas the phase shift can be boosted if k is selected to be positive. In this work, two analog phase shifters with high phase shifts are realized using MCAPNs with positive k and ferroelectric varactors. Depending on whether the layout of the coupled inductors are symmetrical or not, the two phase shifters are respectively designated asymmetric phase shifter and symmetric phase shifter. Among the two phase shifters, the asymmetric one is designed to operate at 10 GHz and fabricated on sapphire substrate. Measurement results show that, when the bias voltage of the ferroelectric varactors are tuned from 0 V to 6 V, the phase shift reaches its maximum at 8.5 GHz with a value of 67.3°. For all bias voltages, the insertion loss is less than 4.5 dB and the return losses are greater than 10 dB from dc to 12 GHz. The reason why the frequency where maximum phase shift occurs shifts from the originally designed 10 GHz to the measured 8.5 GHz is because the capacitance values of the varactors fabricated are larger than the designed values. On the other hand, we develop the fabrication process for ferroelectric varactors with through substrate vias on silicon and apply it to the design of the symmetric phase shifter in this work. The symmetric phase shifter is designed at 2.45 GHz with an expected phase shift of 60°. However, measurement results show that the phase shifter does not exhibit the desired all-pass response. After checking the microphotographs of the fabricated circuit, we find that there is an unexpected piece of metal connection between the two coupled inductors after they go through gold electroplating process. After incorporating this piece of metal connection into the full-wave simultion, the simulated results match the measured results, thus verifying that the unwanted metal connection is the reason when measurement results deviate significantly from the original simulation results. In this work, we successfully design and fabrciate the asymmetric phase shifter, demonstrating the potential for using MCAPNs with k > 0 for implemeting analog phase shifters. As for the symmetric phase shifter, we verify that its failure is due to a specific fault in the fabrication.
Appears in Collections:	[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

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