資料載入中.....
|
請使用永久網址來引用或連結此文件:
http://ir.lib.ncu.edu.tw/handle/987654321/73032
|
| 題名: | 應用於系統級封裝之苯並環丁烯堆疊貫孔、無電鍍鎳金及金覆晶凸塊製程開發;Development of BCB Stacked Via, Electroless Nickel/Gold Plating, and Gold Flip-Chip Bump Processes for System-in-Package Applications |
| 作者: | 盧柏君;Lu, Po-Chun |
| 貢獻者: | 電機工程學系 |
| 關鍵詞: | 苯並環丁烯;覆晶鍵合;系統及封裝;無電鍍鎳金 |
| 日期: | 2017-01-24 |
| 上傳時間: | 2017-05-05 17:39:32 (UTC+8) |
| 出版者: | 國立中央大學 |
| 摘要: | 系統級封裝的理念是將以不同製程技術實現的晶片及元件整合在同一個封裝中，以組成一個系統。覆晶鍵合是一種重要的系統級封裝技術，用於將晶片與載板以長度很短的覆晶凸塊來連接；與傳統的鎊線相較，覆晶凸塊具有低寄生電感的優點，適合高頻應用。在載板端，本論文開發了苯並環丁烯（BCB）堆疊貫孔製程及電鍍金覆晶凸塊製程。在晶片端，我們實作了無電鍍鎳金於晶片接腳。最後，我們透過金－金熱壓合，將晶片覆晶鍵合於載板上。
BCB具低介電係數、高崩潰電壓等特性，相當適合用作覆晶鍵合載板端的介電材料。為實現以BCB為介質的微帶線結構，本論文開發了BCB堆疊貫孔技術。我們將BCB旋佈、曝光、顯影及烘烤固化這些步驟重覆三次，來分層堆疊獨立製作每層的貫孔，成功實現貫孔於總厚度約為28 μm的BCB介電層。我們使用此堆疊貫孔技術，實現以BCB為介電層、金為金屬層的微帶線架構。量測結果顯示，微帶線在頻率為20 GHz時，其單位線長植入損耗皆小於0.15 dB/mm。而用實作尺寸代入電磁模擬軟體模擬，與量測結果擬合，可推論BCB介電常數為2.65、損耗正切為0.002。另外，透過量測可知試片上有部分微帶線製作失敗；貫孔形狀不均應為失敗的原因。未來貫孔可改成乾蝕刻方式製作，以得到均勻的貫孔形狀，使貫孔良率提升。
在覆晶鍵合技術實現方面，我們把以TSMC 0.18-μm CMOS製程實現之50-Ω微帶線，透過覆晶方式與藍寶石載板上的共平面波導傳輸線連接。我們以無電鍍鎳金技術在CMOS晶片的鋁墊上依序沉積鎳及金，而載板上約12 μm高的覆晶凸塊則以電鍍金方式實現，最後以熱壓合方式將晶片鍵合至載板上。量測結果顯示，在10 GHz時，覆晶後的傳輸線返回損耗仍大於20 dB。扣除晶片上微帶線及載板上共平面波導線的損耗，我們可計算出覆晶單側接點於10 GHz時總共貢獻約0.04 dB的植入損耗。
在本論文中，我們開發了有效製作BCB堆疊貫孔的製程，並藉以實現了以BCB為介電層的低損耗微帶線。另外，我們實作了可於0.18-μm CMOS晶片接腳層無電鍍鎳金之製程，並開發於藍寶石載板上之電鍍金覆晶凸塊，最後成功地以金－金熱壓合方法鍵合晶片與載板；所實現之覆晶接點在微波頻段具低植入損耗。未來我們可結合這些製程，完成載板以BCB為微帶線介電層之系統級封裝模組。
;The concept of System-in-Package (SiP) is to integrate chips and components implemented by different process technologies into one package and form a system. Flip-chip bonding is an important SiP technology, which is used to connect the chip and carrier substrate with short flip-chip bumps. Compared with the conventional bond wires, flip-chip bumps possess lower parasitic inductance and are more adequate for high-frequency applications. In this work, on the carrier-substrate, benzocyclobutene (BCB) stacked via and electroplated gold flip-chip bump processes are developed. On the chip side, the technique of electroless nickel-gold plating on the chip pads is implemented. Finally, the chip is flip-chip bonded onto the carrier by gold-gold thermo-compressive bonding.
BCB is a dielectric material with low dielectric constant and high breakdown voltage, making it suitable for dielectric layers on flip-chip carrier substrates. To realize microstrip structure with BCB as the dielectric layer, we develop the BCB stacked via process. Spin-coating, exposure, developing, and curing of BCB are repeated three times to fabricate via holes on the three stacked BCB layers. Vias are successfully fabricated on the BCB dielectric layer, which has a total thickness of about 28 μm. The stacked via process is then used in the fabrication of microstrip lines with BCB as its dielectric and gold as its metal. The measurement results of the microstrip lines show that the insertion loss per unit length at 20 GHz is less than 0.15 dB/mm. By fitting the full-wave simulation results with the measurement results, it is found that the dielectric constant and loss tangent of the BCB are 2.65 and 0.002, respectively. Examining the measurement results, we find that the fabrication of some of the transmission line has failed. We believe that the failure is due to that the shape of the fabricated BCB vias is not uniform as its originally designed. In the future, the BCB vias can be fabricated using dry etching to obtain uniform via shapes and improve the yield.
On the implementation of flip-chip bonding, we connect chips that contain 50-Ω microstrip lines realized using TSMC 0.18-μm CMOS technology with coplanar waveguide (CPW) transmission lines on a sapphire carrier substrate by flip-chip bumps. We subsequently deposit nickel and gold on the aluminum pads of the CMOS chips by electroless plating. On the carrier substrate, the flip-chip bumps with about 12-μm height are fabricated using gold electroplating. The chips are then flip-chip bonded onto the carrier by gold-gold thermocompressive bonding. Measurement results show that, at 10 GHz, the return loss of the flip-chip bonded transmission line is still greater than 20 dB. By subtracting the losses of the microstrip on the chip and CPW lines on the carrier, it is calculated that the insertion loss contributed by flip-chip contact at single side is 0.04 dB at 10 GHz.
In this thesis, we develop an effective fabrication process for making stacked vias on BCB and successfully use the process to realize low-loss microstrip lines with BCB as the dielectric layer. In addition, we implement an electroless plating process to deposit nickel/gold on pads of CMOS chips. We also develop an electroplating process to fabricate gold flip-chip bumps on sapphire carrier substrates. Finally, we demonstrate the gold-gold thermocompressive bonding to connect the chips and carrier substrates, realizing low-loss flip-chip contacts at microwave frequencies. In the future, we can combine these processes to fabricate SiP modules on carriers with BCB as the dielectric layer. |
| 顯示於類別: | [電機工程研究所] 博碩士論文
|
文件中的檔案:
| 檔案 |
描述 |
大小 | 格式 | 瀏覽次數 |
|---|
| index.html | | 0Kb | HTML | 497 | 檢視/開啟 |
|
在NCUIR中所有的資料項目都受到原著作權保護.
|
