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    Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/74971

    Title: 針對電流控制模式直流降壓轉換器之佈局自動化整合工具;Automatic Layout Synthesis Tool for DC-DC Current-Mode Buck Converter
    Authors: 許昕茹;Hsu, Hsin-Ju
    Contributors: 電機工程學系
    Keywords: 電流控制模式;直流降壓轉換器;自動化
    Date: 2017-08-21
    Issue Date: 2017-10-27 16:14:19 (UTC+8)
    Publisher: 國立中央大學
    Abstract: 在現代科技發達的生活環境裡,充滿著各式各樣由混合訊號晶片所構成的產品,例如: 可攜式電子產品(平板、智能手環)、醫療設備(血壓計)、電信通訊產品(手機、網路分享器)以及車用電子產品(防盜保全系統)等等。尤其近年來,伴隨大眾需求度的上升,從產品設計到上市的周期亦隨之縮短,而電子自動化工具便成為加快生產流程中不可或缺的關鍵。
    雖然目前數位電路的自動化工具已發展得相當成熟,市面上也可以看到許多EDA 工具協助設計者,然而,類比混合訊號自動化設計工具卻十分少見,其中最大主因為類比電路對於訊號反應相當敏感,大多數還是依靠設計者人為完成完整佈局設計。因此,類比電路設計往往成為混合訊號單晶片(SoC)發展的瓶頸,而學術界也持續努力發展相關針對類比電路的自動化工具。
    為了提升電路設計效能及縮短設計時間,本論文針對電流控制模式直流降壓轉換器電路發展一個佈局自動化整合工具,此流程能完整將電路從輸入規格到最終佈局及繞線自動化產生。整套流程以C++及Tcl/Tk 程式語言實現,且自動化佈局的過程能在Laker環境下執行,不僅可成功通過DRC 與LVS 的驗證,同時Post-layout 的模擬結果也能達到預期的電路效能。
    ;In our days, lots of electronic product are made of analog/mixed-signal (AMS) intergrated circuits (ICs), such as portable devices, medical equipment, communication product and automobile electronics etc. Nowadays, with the growing demands for portable devices, Time-to-Market cycle still keeps shrinking. Electronic design automation (EDA) tools are the keys to speed up the device process.
    There are many existing EDA tools for digital circuits on the market. However, the EDA tools for AMS circuits are still not popular. Because analog circuits are often sensitive to small signals response, their layouts are often manually designed by experienced designers. Therefore, AMS circuit design has become the bottleneck in SoC design flow.
    In order to increase the circuit performance and shorten design process, we perpose an automatic layout synthesis tool for DC-DC current-mode control buck converters in the thesis. This synthesis tool is able to generate the final layout of the target circuit automatically from given specification. The design environment is developed with C++ and Tcl/Tk programming language. The required layout can be generated in Laker automatically and pass the DRC/LVS verification. The post-layout simulation results also satisfy the required specification.
    Appears in Collections:[電機工程研究所] 博碩士論文

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