負電容場效電晶體於超低功耗應用之研究與分析;Investigation and Analysis of Negative Capacitance Fets for Ultra-Low Power Applications

NCUIR > College of Electrical Engineering & Computer Science > Department of Electrical Engineering > Research Project > Item 987654321/78747

Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/78747

Title:	負電容場效電晶體於超低功耗應用之研究與分析;Investigation and Analysis of Negative Capacitance Fets for Ultra-Low Power Applications
Authors:	胡璧合
Contributors:	國立中央大學電機工程學系
Keywords:	負電容場效電晶體;邏輯電路;變異度;可靠度;鐵電材料;Negative capacitance FET (NCFET);Logic;Variability;Reliability;Ferroelectric layer
Date:	2018-12-19
Issue Date:	2018-12-20 13:46:45 (UTC+8)
Publisher:	科技部
Abstract:	在此計晝中，我們將對負電容場效電晶體及其邏輯電路，包含靜態及動態邏輯電路，其元件及電路的變異度及可靠度進行全面性的分析及研究。我們將研究鐵電層(Ferroelectric layer) 的材料參數，包含剩餘極化(Remanent polarization)、橋頑電場(Coercive electric field)及鐵電層厚度，對負電容場效電晶體及邏輯電路之影響。我們也將研究鐵電材料搭配不同的元件結構，如平面式場效電晶體、超薄層場效電晶體及鮨狀場效電晶體的元件及電路特性。本質製程變異度將考慮隨機摻雜擾動(Random dopant fluctuation)、線邊緣粗糙(Line-Edge-Roughness)及功函數變異(Work Function Variation)，對元件及邏輯電路的影響。可靠度將研究隨機電報雜訊 (Random telegraph noise)的影響。在第一年裡，我們將建立負電容場效電晶體的數值模擬架構; 接著在第二年，我們將延伸第一年的模擬架構，利用查找表(lookup table)的Verilog-A模型，建立負電容場效電晶體的電路模擬架構。第三年將發展適用於超低功耗的可容忍變異度及可靠度(Variability and reliability-tolerant)的負電容場效電晶體元件及電路共同設計，以提升負電容場效電晶體的能量效率(Energy efficiency)。 ;In this sub-project, we conduct a comprehensive study of the negative capacitance FET (NCFET) device and circuit considering the variability and reliability analysis for ultra-low power applications. Three device structures including planar MOSFET, ultra-thin-body (UTB) SOI MOSFET, and FinFET integrated with ferroelectric layer will be analyzed in this project. The impact of remanent polarization, coercive force, and ferroelectric layer thickness on the NCFETs and logic circuits will be analyzed. Intrinsic process variations including random-dopant fluctuation (RDF), line-edge-roughness (LER), and work function variation (WFV) will be considered to examine the device characteristics and leakage-delay analysis for NCFET and logic circuits. For reliability analysis, random telegraph noise (RTN) will be investigated for NCFET device and logic circuits. In the first year, we will establish the numerical simulation framework for NCFET devices, then in the second year, we will extend this framework combined with the lookup table Verilog-A model to simulate the circuit performance for NCFET. In the third year, the variability- and reliability-tolerant design will be investigated to improve the leakage-delay performance and switching energy of NCFET devices and logics for ultra-low power and energy efficient applications.
Relation:	財團法人國家實驗研究院科技政策研究與資訊中心
Appears in Collections:	[Department of Electrical Engineering] Research Project

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