DVB-T數位電視廣播接收機之數位前端與同步系統設計與實現; Design and Implementation of Digital Front-End and Synchronization System for DVB-T Receiver

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题名:	DVB-T數位電視廣播接收機之數位前端與同步系統設計與實現;Design and Implementation of Digital Front-End and Synchronization System for DVB-T Receiver
作者:	趙德安;Te-an Chao
贡献者:	通訊工程研究所
关键词:	正交分頻多工;數位前端;載波頻率偏移;取樣頻率偏移;Sampling Frequency Offset;Carrier Frequency Offset;Digital Front-End;OFDM
日期:	2007-06-27
上传时间:	2009-09-22 11:20:42 (UTC+8)
出版者:	國立中央大學圖書館
摘要:	DVB-T數位電視廣播採正交分頻多工(OFDM)調變技術，此技術具有高頻譜效率、抗多重路徑干擾等優異特性。在使用超外差射頻接收機架構之正交分頻多工接收系統中，類比中頻訊號利用帶通取樣技術將類比訊號取樣為數位中頻訊號，此訊號經過移頻與低通濾波後，利用費洛濾波器轉換為基頻取樣率，此一過程稱為數位前端。然而，數位前端過程中，如果發生符元時間誤差、載波頻率誤差以及取樣率誤差，對ODFM系統效能影響甚大，所以同步對接收端而言是極為重要的，而同步動作主要依賴循環字首訊號重複之相關性估測出誤差，並由數位前端補償。本論文將對數位前端之費洛濾波器係數做探討，並利用SIR對每根子載波的關係判斷ICI嚴重程度，藉以得知費洛濾波器係數優劣；並針對各項同步提出估測方式，建立適用於DVB-T接收機之同步系統。最後以Veriolog語言撰寫數位前端與同步系統，搭配ModelSim軟體進行模組功能驗證，並實現於FPGA平台。 The digital video broadcasting – terrestrial (DVB-T) has adopted the orthogonal frequency division multiplexing (OFDM) which exhibits superior characteristics in terms of efficiency in spectral utilization and combat multi-path effect. In an OFDM receiver using superhetrodyne architecture, the analog IF output signal of the RF module is sampled and converted to a digital IF signal at an IF sampling rate adhered to bandpass sampling theorem. A digital front-end incorporating spectral shifting, low-pass filtering and sampling rate conversion using farrow structure is then used to convert the digital IF signal to the baseband signal. OFDM systems are deeply affected by timing offset, carrier frequency offset and sampling frequency offset, hence the synchronization system is essential in receiver. The estimation of synchronization errors is mainly based on the correlation of cyclic prefix and the compensation is done within the digital front-end. In this thesis, we discuss how to discriminate good coefficient of farrow filter from bad ones by ICI effect due to the aliasing. We also proposed schemes for the synchronization system for DVB-T receiver. At the end of this thesis, we implemented the digital front-end and synchronization systems in hardware with Verilog language. The implementation is verified with Modelsim tool and real-time implementation on FPGA hardware.
显示于类别:	[通訊工程研究所] 博碩士論文

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