高密度 4T 與 6T 低溫鰭式場效電晶體靜態隨機存取記憶體;High Density 4T and 6T Cryogenic FinFET SRAM

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Title:	高密度 4T 與 6T 低溫鰭式場效電晶體靜態隨機存取記憶體;High Density 4T and 6T Cryogenic FinFET SRAM
Authors:	劉昌儒;Liu, Chang-Ju
Contributors:	電機工程學系
Keywords:	低溫金氧半場效電晶體;靜態隨機存取記憶體;積層型三維堆疊;後段製程;能量效率
Date:	2021-11-29
Issue Date:	2021-12-07 13:27:09 (UTC+8)
Publisher:	國立中央大學
Abstract:	隨著製程微縮技術的推進，降低電源電壓與臨界電壓會導致漏電功率嚴重增加，使得互補式金氧半場效電晶體(CMOS)電路的性能受到限制，此外在先進節點技術下，內部金屬導線的微縮會造成導線電阻大幅增加，進而降低電路的效能表現。而低溫 CMOS(Cryo-CMOS)是一個極具潛力的解決方式，元件可以透過操作在超低溫下來提高性能表現與降低電源功率。因此本研究透過 TCAD 軟體的Mixed-Mode 模擬，同時考慮內部導線模型(π-3 Model)，研究 300K 與 77K 下，4T與 6T 靜態隨機存取記憶體(SRAM)的讀寫穩定度和速度等特性。研究結果顯示與 300K 的 6T SRAM 相比，4T SRAM 操作在 77K 時，在面積上縮減了 20.3%、讀取時間減少 44%、寫入時間減少 46%、寫入穩定度提高了 2.3倍、能量延遲積(EDP)減少了 53%。本論文也探討了利用 Transistor-Level 積層型三維堆疊的方式來設計 SRAM，在三維堆疊的設計中，將 P 型與 N 型電晶體製作在不同的平面上，可以調整製作流程並獨立優化電晶體特性，不但可以縮小 SRAM 的單元面積也可以減少內部導線的繞線長度，使字元線及位元線的電阻電容值降低。研究結果顯示 77K 下兩層設計的積層型 4T SRAM 與 300K 下的 6T 一層的設計相比可以改善 62%讀取時間、69%寫入時間及 77%能量延遲積。本篇論文提出具有高能量效率與面積小的兩層積層型三維 4T SRAM，可增加在邊緣運算裝置的應用潛力。;As the technology scaling continues, it is getting more challenging to improve the CMOS power performance by reducing the supply voltage and threshold voltage without prohibitively increasing its leakage power. Moreover, continued scaling of the metal interconnection geometry increases wire resistance which degrades the circuit performance in advanced technology nodes. Cryo-CMOS has emerged as a highly promising solution to improve performance and power efficiency by operating the devices at ultra-low temperatures. Therefore, the thesis explores the performance of SRAM at lower temperatures using TCAD Mix-Mode simulations coupled with the interconnect π-3 model. This thesis analyzes the read stability, write stability, and speed for 6T and 4T SRAM cells at 300 K and 77 K. Compared to 6T SRAM cell at 300K, 4T SRAM cell at 77K shows 20.3% cell area reduction, 44% reduction in read access time, 46% improvement in write time, 2.3× improvement in write stability, and 53% reduction in energy-delay product (EDP). The thesis also explores the design methodology of SRAM cell with transistor-level monolithic 3D integration. In transistor-level M3D design, p-type and n-type transistors are fabricated on different layers, which can be optimized separately. The 3D integration reduces the SRAM cell area and reduces the interconnect lengths, which is beneficial for lowering wire routing resistance and capacitance. Compared to the 1-tier 6T SRAM cell at 300K, the monolithic 2-tier 4T SRAM cell shows 62% improvements in read access time, 69% improvements in time to write, and 77% improvements in EDP at 77K. The energy- and area efficiency of 2-tier 4T SRAM cell enables intelligent functionalities for the energy-constrained edge computing devices.
Appears in Collections:	[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

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