開啟製程相似檢查方法在組裝超級塊上以最小化額外的寫入延遲;Enable Process Similarity Check Method on Grouping Super Block to Minimize the Extra Write Latency

NCUIR > College of Electrical Engineering & Computer Science > Executive Master of Computer Science and Information Engineering > Electronic Thesis & Dissertation > Item 987654321/89746

Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/89746

Title:	開啟製程相似檢查方法在組裝超級塊上以最小化額外的寫入延遲;Enable Process Similarity Check Method on Grouping Super Block to Minimize the Extra Write Latency
Authors:	曾釋弘;Tseng, Shih-Hung
Contributors:	資訊工程學系在職專班
Keywords:	3D NAND快閃記憶體;製程相似;超級塊;額外寫入延遲;3D NAND Flash Memory;Process Similarity;Super Block;Extra Write Latency
Date:	2022-07-04
Issue Date:	2022-10-04 11:58:21 (UTC+8)
Publisher:	國立中央大學
Abstract:	3D NAND閃存已成為數據存儲設備最流行的介質，並不斷擴大其市場和SSD等各種高速數據訪問需求領域的應用。為了最大化數據吞吐量，採用了NAND flash芯片內部不同平面的數據塊（block）和不同通道的NAND flash芯片並行訪問的概念，稱為超級塊（super block）。一個成功的超級塊訪問需要所有數據塊一起完成它們的工作才能完成操作。但是，這裡提出了額外延遲的問題。因為，即使在同一個 NAND 閃存芯片中，由於 NAND 閃存製造工藝，這些塊也會出現不同的特性和延遲。如果將最快和最慢的塊組裝到同一個超級塊中，則額外的延遲會顯著影響寫入性能。本研究提出了一種考慮塊之間製程相似性（process similarity）的超級塊組裝方法，通過創建、識別塊的“特徵序列（eigen-sequence）”來組裝最相似的塊，以減少超級塊的額外延遲。此外，這種方法允許我們有選擇地組裝一個快速或慢速的額外延遲減少的超級塊。根據寫入需求的不同優先級，上層可以為需求分配相應速度等級的超級塊，從而進一步提升寫入性能。;The 3D NAND flash memory has become the most popular media for data storage devices, and it keeps expanding its market and applications like SSD for various high-speed data access demand fields. In order to maximize the data throughput, the concept of parallel access of data block in different planes inside the NAND flash chip and NAND flash chips in different channels is employed, which is called a super block. A successful super block accessing needs all the blocks finish their works together to complete the operation. However, the problem of extra latency is raised here. Because, even in the same NAND flash chip, the blocks appear different characteristics and latency with one another due to NAND flash fabrication processes. If the fastest and slowest blocks are assembled into the same super block, the extra latency conspicuously influences the write performance. This study presents a super block assembly method considering of process similarity between blocks by creating, identifying the ”eigen-sequence” of blocks for the assembly of most similar blocks to reduce the extra latency for super blocks. In addition, this method allows us selectively assemble a fast or slow of extra latency reduced super block. Depending on the different priority of write demand, the upper level can assign the super block with an appropriated speed class to the demand, and therefore further enhance the write performance.
Appears in Collections:	[Executive Master of Computer Science and Information Engineering] Electronic Thesis & Dissertation

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