| 摘要: | 在有線通訊中，由於傳輸端雙絞線傳送資料時可能因為彼此間空間距離過近，導致與其它線發生電感性或電容性耦合的現象，造成其它對線耦合出電流電壓的訊號，產生串音干擾的現象( crosstalk )，而網路傳輸線裡會有四對的雙絞線，因此在四對線中彼此都會互相干擾，影響其接收訊號的完整，顯示了近端串音干擾消除器( near end crosstalk canceller ) 之必要性。本論依據 IEEE 802.3 bz™-2016[1] 規範標準設計乙太網路之近端串音干擾消除器，處理訊號在接收端受到其它對雙絞線的串音干擾之影響，並消除錯誤的訊號。本論文針對串音干擾通道模型所採用的濾波器以相對於傳統有限脈衝響應濾波器（Finite impulse response filter）成本較低的無限脈衝響應濾波器(infinite impulse response filter)來設計消除器，因為隨著通道效應拉長，有限脈衝響應濾波器需跟著拉長才能達到可接受之串音干擾消除效果，因此需要之乘法器數量也會隨之增長，造成電路成本提高，因此在電路成本越來越受到重視的情形下，無限脈衝響應濾波器將會是效能與成本考量上的最佳解。而演算法部分則參考既有文獻之方法尋找適合實現的演算法，並對演算法部分進行改良，使其演算法效能提升，以達到良好的串音消除效果，消除傳送端傳輸線內部的串音干擾訊號。硬體實現上，使用Verilog HDL描述與模擬，並透過SMIMS VeriEnterprise Xilinx FPGA驗證電路功能，再經由Design compiler與IC compiler來驗證在製程為TSMC-40nm下之電路功能。;In wireline communications, due to the fact that the twisted pair at the transmission end may be too close to each other when transmitting data, other lines may be inductively or capacitively coupled, causing other lines to couple current and voltage signals, resulting in crosstalk interference. phenomenon ( crosstalk ), There are four pairs of twisted pairs in the network transmission line, so the four pairs of lines will interfere with each other, affecting the integrity of the received signal, showing the necessity of a near-end crosstalk canceller. This paper designs a near-end crosstalk canceller for Ethernet networks based on the IEEE 802.3 bz™-2016[1] standard to deal with the influence of crosstalk interference from other pairs of twisted pairs on the signal at the receiving end, and eliminate the wrong signal. The filter used in this paper for the crosstalk interference channel model is an infinite impulse response filter with a lower cost than the traditional finite impulse response filter. Because as the channel effect lengthens, the finite impulse response filter needs to be lengthened to achieve an acceptable crosstalk cancellation effect, so the number of required multipliers will also increase, resulting in an increase in the circuit cost. With increasing attention, an infinite impulse response filter will be the best solution in terms of performance and cost. The algorithm part refers to the method of the existing literature to find a suitable algorithm for implementation, and improves the algorithm part to improve the performance of the algorithm, so as to achieve a good crosstalk cancellation effect and eliminate the crosstalk in the transmission line at the transmitting end.
Regarding the hardware implementation, first the Verilog HDL description is employed and the related simulations ,are conducted, then verify the circuit function through SMIMS VeriEnterprise Xilinx FPGA, and finally verify the circuit function under the TSMC-40nm process through Design Compiler and IC Compiler. |
