具有通道熱電子注入編程能力的40nm 4kb 1T OTP陣列的設計和實現;Design and Implementation of a 40nm 4kb 1T OTP Array with Channel Hot Electron Injection Programming Scheme

NCUIR > College of Electrical Engineering & Computer Science > Graduate Institute of Electrical Engineering > Electronic Thesis & Dissertation > Item 987654321/90832

Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/90832

Title:	具有通道熱電子注入編程能力的40nm 4kb 1T OTP陣列的設計和實現;Design and Implementation of a 40nm 4kb 1T OTP Array with Channel Hot Electron Injection Programming Scheme
Authors:	葉宥鋐;YE, YOU-HONG
Contributors:	電機工程學系
Keywords:	一次編程記憶體;多位元存儲;單一電晶體單元;記憶體陣列;One-time programming memory;multi-bit storage;1T unit-cell;memory array
Date:	2022-10-25
Issue Date:	2023-05-09 18:09:38 (UTC+8)
Publisher:	國立中央大學
Abstract:	隨著電子裝置記憶體容量需求增加，應用於高容量密度記憶體、低功耗、高安全性晶片需求大增，一次性可編程 (OTP) 存儲器變得越來越重要，防止存儲資料不被竄改，提供安全的密鑰存儲，相對於一般光罩式唯讀記憶體 (Mask ROM) 做比較，有更大彈性上使用，可在晶片製造後做代碼更改，有效降低除錯及更新的時間，操作速度夠快，可以直接執行代碼，無需將代碼複製到片上隨機存取記憶體 (RAM) 來執行，縮短啟動時間，使用電荷儲存 (charge storage) 操作機制，相對於反熔絲 (Anti-fuse OTP)、電子熔絲 (efuse OTP) 有較低操作電壓與面積小，低功率消耗的優勢。本論文中分四個部分分別為解碼器、記憶體陣列、感測放大器與邏輯判斷電路，解碼器在不同操作條件下選定陣列中的位址，給予操作電壓值，確保未選到位址接地不影響編程中的元件，感測放大器採用電流感測器放大器模式進行讀取，能讀取小電流且很大感測裕度，更準確的讀取資料。本研究設計容量為4kb的OTP記憶體陣列，在編程上有快的操作速度(1μs)與較低的編程電壓(1.8V)，單位元面積僅需0.1452μm2，面積小的之優勢。透過不同編程電壓，來達到多位元存儲，來增加記憶體容量，在讀取時可以達到很低位元錯誤率為1.76%，此記憶體陣列能在攝氏125度下烘烤740小時後仍能操作。 ;As demand of memory capacity for increase in electronic devices, demand of highly-dense memory, low-power, and highly-secured chips also increases. One-Time Programming (OTP) memory becomes more and more important. To prevent stored data from being hacked, a secure -key storage is necessity. In comparison with the Mask ROM, One-Time Programming (OTP) memory has more flexibility. It can make code changes after the chip has been manufactured, effectively reducing time for debugging and updating. Hence, the operation speed is faster. It also eliminates the need to duplication of codes for on-chip random access memory (RAM), which reduces startup time. To support this functionality, a charge storage operating mechanism is used by users to program the OTP cell. In comparison with the anti-fuse (OTP) and electronic fuse (efuse OTP), our single-transistor charged-based one-time Programming (OTP) memory has the advantages of lower operating voltage, smaller area, and lower power consumption. The OTP MACRO is divided into four parts: decoder, memory array, sense amplifier and logic control circuit. The decoder selects an address in the array under different operating conditions. It also applies the operating voltages to ensure that the unselected cells area not affect by the operation voltage under the selected one. The sense amplifier uses the current sensing mode for readout the information stored in the 1T OTP cell, which can read a small current amount with a large sensing margin so as to read more accurately. This work designs an OTP memory array with the capacity of 4-k cells, which shows advantages of fast operation speed (1s) and low programming voltage (1.8V) in programming. Another benefit of this OTP memory array is smaller cell-size. The unit area is only 0.1452μm2 per cell. Furthermore, to increase memory capacity aggressively, 3-bits-per-cell storage is achieved through different incremental programming voltages. This array also achieves a low bit error rate of 1.76% when random-access is performed. As a result, reliabilities are also evaluated, the memory array can keep information after baked in 740 hours at 125 Celsius.
Appears in Collections:	[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

Files in This Item:

File	Description	Size	Format
index.html		0Kb	HTML	77	View/Open

社群 sharing

Loading...