在此主要的研究目標是設計一適用於ATSC VSB時脈回復電路之全數位延遲線迴路。此電路有幾個特點 : 第一、整個電路為全數位化，可直接使用硬體語言(Verilog) 描述其功能，且使用自動化佈局工具實現。第二、此電路的主要架構為一串128級的反相器，非常簡單，所佔的面積很小。第三、其偵測電路只有一個D型正反器判斷相位的領先或落後，此方式也很簡易且判斷速度符合規格要求。第四、為了增加迴路對時脈抖動的抵抗能力，我們加上一個信心計數器來確定偵測電路所判斷的值。第五、使用有限狀態機 (finite state machine) 控制整個迴路。 我們透過C和Verilog的模擬驗證其可行性，且使用TSMC 0.35μm 1P4M的製成實現整個硬體架構。整個電路只使用了近3000個邏輯閘，晶片面積為524μm×517μm (不包含I/O 單元) 。晶片測試結果也符合規格的要求，其所能產生之相位解析度為370ps至810ps之間，時脈所產生之抖動在270ps之內。 In this thesis, an all-digital delay locked loop for ATSC VSB timing recovery has been proposed and implemented. The proposed architecture has the following distinguishing features. First, the all the circuit is digitalized. Its functions have been described by hardware description language (Verilog). Auto place and route tool are used to implement the circuit. Second, the main structure of this circuit is a string of 128 inverters. It is very simple to accomplish and the area is small. Third, it uses only the lead-lag decision for the DLL instead of the phase difference information for the DLL to minimize the hardware complexity. Forth, it takes the confidence counter to improve the stability against the clock jitter and environment noise. Fifth, it uses the finite state machine to control the whole circuit. We use C language and Verilog language to simulate the architecture and verify the functionality. Then, the chip had been designed and implemented using TSMC 0.35μm 1P4M technology. The gate count of 3000 reconfirms the simplicity of the architecture. The area of the chip is 524μm×517μm (not including I/O pad). Finally, the test result fits the required specification It products a phase resolution between 370ps to 810ps, and the clock jitter is lower than 270
