近年來無線通訊產業快速發展，關鍵技術日趨成熟，但是射頻無線積體電路的成本仍然偏高，為了降低製作成本及整合數位、類比電路，採用低價格的CMOS製程做設計，已是未來的趨勢。射頻無線通訊的收發端中，頻率合成器是提供載波的重要架構，若採用CMOS製程做設計，仍有許多困難須克服，所以我們嘗試以不同的系統架構及電路來解決此一問題。 在此論文中我們使用TSMC CMOS 0.35μm製程，設計一個適用於Multi-GHz頻率合成器中所使用的壓控振盪器 (Voltage - controlled oscillator)、倍頻器(Frequency doubler)及除頻器(Divider)的電路設計。在晶片設計上，系統工作電壓為2V，壓控振盪器工作頻率為2.5GHz，相位雜訊為-109dBc，功率消耗為20mW；倍頻器工作頻率為5 GHz，相位雜訊為-97dBc，功率消耗為4mW。在除頻器部份，採用CMOS 0.25μm製程設計，我們提出一個全新架構高速低功率除頻器，經過模擬後可操作的頻率可達19 GHz，並且適用於各種除數，包括奇數及偶數，功率消耗低於4.5mW。此論文解決了目前高速頻率合成器所遇到的一些瓶頸，使CMOS製程更適用於射頻無線通訊系統收發端，加速在高頻下數位及類比電路之整 Frequency synthesizer is the important component of the carrier in RF wireless architecture. But at Multi-GHz , PLLs still have many issue to be overcame. In this thesis, we implement a VCO(voltage-controlled oscillator), frequency doublers and frequency dividers applying for Multi-GHz frequency synthesizers in TSMC 0.35 μm 1P4M CMOS technology. In the chip, supply voltage is 2V and VCO phase noise is —109dBc/Hz at 5MHz offset with 4 quadrature phasors for 2.5GHz, and the power consumption is 20mW. The phase noise of the frequency doubler is —97dBc/Hz at 5MHz offset for 5GHz, and the power consumption is only 4mW. The central frequency of the divider is 4GHz and locking rang is about 300MHz. The novel high frequency and low power consumption dividers are implemented in CMOS 0.25μm technology. The operating frequency of the dividers is at 19GHz by simulation with RF Model. The divisor of the dividers can be odd or even, and power consumptions are below 4.5mW. The thesis overcomes some difficulties of the high frequency synthesizer applying for RF wireless transceiver structure.
