我們在此提出一多模組相位同步技術。多模組的相位同步是個重要部分對於SOC系統的環境。所提出的同步技術目前是適合應用於整合自動測試機臺。此同步技術的優點是可很容易的增減所需同步模組的個數。同時能提供穩定同步且可調整的時序。而有了此同步且可調整的時序，我們可以用以取代原自動測試機臺的時序產生器。而此同步的機制可以簡化且縮減傳統所需的時序校正所需且冗長的時間。同步機制的模擬是先採用C語言描述加以模擬其機制動作，用以檢視其機制的運作。再來以Verilog硬體描述來模擬硬體實現的環境。模擬的環境設定成接近實際的運作環境。而同步機制所需的相位產生器是以TSMC 1p4m 0.35um 的製程技術設計製作。而其量測的結果可驗證其精細的相位解析度。 In this thesis, we have proposed a novel methodology for multi-module synchronization. The multi-module synchronization is an important feature for SOC (system on a chip). The proposed synchronization methodology can also be fitted into the integration of ATE (automatic test equipment). The advantage of this methodology is easy to expand the number of modules without significant effort for the modification. It also provides highly stable synchronous timing and adjustable phase. With these, the synchronization mechanism can replace the original timing generator for the ATE. The synchronization mechanism also can simplify the con-ventional timing calibration process. The system simulation of the synchronization methodology is done in C language and Verilog. The simulation environment is set close to the condition of real environment. The component of multi-phase generator is designed with TSMC 1p4m 0.35um technology. The measurement results verify the generation of fine timing.
