近年來隨著半導體產業的蓬勃發展，產品應用上所需之資料傳輸頻寬也不斷提高，傳輸介面中，並列傳輸介面因為成本較高的問題，已逐漸被高速串列傳輸介面所取代，隨著串列傳輸系統的傳輸速率提升，抖動對資料的影響佔比越加顯著，在電路的設計上也更加有難度，因此在時脈與資料回復電路的中，優化抖動容忍度並且降低追鎖抖動將成為設計首要目標。 本論文實現一具有資料序列偵測器之6 Gbps全速率時脈與資料回復電路，提出資料序列偵測器的做法，針對相位追蹤補償相位偵測器在遇到長時間不轉態的輸入資料時，會產生與輸入資料不轉態資料筆數相同之長輸出脈波訊號，使得系統有較大的追鎖抖動的問題做改善，資料序列偵測器在偵測到長0或長1的資料序列時，會產生控制訊號，將電荷幫浦的充放電路徑的開關關閉，藉此降低還原時脈的抖動量。透過結合資料序列偵測器與相位追蹤補償相位偵測器的做法，成功達到降低追鎖抖動與良好的抖動容忍度表現。本論文使用TSMC 90 nm 1P9M (TN90GUTM) CMOS 製程實現，操作電壓為1.0 V，輸入資料速率為6 Gbps，輸出還原時脈訊號為6 GHz，當輸入PRBS31的資料時，開啟資料序列偵測器下的還原時脈之抖動峰對峰值為9.24 ps，抖動方均根植為3.14 ps，與未開啟資料序列偵測器的還原時脈抖動峰對峰值相比於後模擬中有27.24%的改善量，功率消耗為33.00 mW，核心電路面積為0.087 mm2，晶片面積為1.59 mm2。 ;In recent years, with the rapid development of the semiconductor industry, the requirement of data transmission bandwidth for product applications has also increased. Among the transmission interfaces, the parallel transmission interface has gradually been replaced by the high-speed serial transmission interface due to cost-related issues. With the increasing transmission rate of the serial transmission interface, the impact of jitter on the data becomes more significant, and circuit design becomes more challenging. Therefore, optimizing jitter tolerance and reducing jitter in the clock and data recovery circuit will be the primary design goal. This thesis implements a 6 Gbps full-rate clock and data recovery circuit with a data pattern detector. The proposed CDR presents a data pattern detector(DPD) which improved the drawback of phase tracking compensation phase detector(PTCPD). When input data has a long consecutive identical digits(CID), PTCPD will generates a long pulse-width output signal with the same bits of consecutive non-transition data. This case will increase the recovered clock jitter. When DPD detects long sequences of 0 or 1 data, it generates control signal which disables the charging and discharging path of the charge pump. This reduces the jitter of recovered clock. By using the DPD and the PTCPD, the circuit achieves improved jitter of recovered clock and robust jitter tolerance performance. The chip is fabricated by TSMC 90 nm 1P9M (TN90GUTM) CMOS process. With a supply voltage of 1.0 V, input data rate of 6 Gbps, and produces an output recovered clock signal at 6 GHz. When the PRBS31 data is inputted, the post-layout simulation results of the recovered clock peak-to-peak jitter is 9.24 ps and a root mean square jitter is 3.14 ps. The proposed CDR with DPD represents a 27.24% improvement in recovered clock peak-to-peak jitter compared to the CDR without DPD. The power consumption is 33.00 mW. The core area is 0.087 mm2, and the chip area is 1.59 mm2.
