| 摘要: | 本論文主要研究使用開關電容陣列及波形整型得到較低相位雜訊的本地振盪源。第二章的主要內容為操作在K頻段及Ka頻段且使用5位元開關電容陣列來達到高可調範圍的差動壓控振盪器。第三章則是先提及將輸出波形整型對相位雜訊的影響，接著再介紹操作在X頻段的F23類差動壓控振盪器，以及提出三顆分別使用背閘極耦合、閘極端電容耦合和汲極端電容耦合的F23類四相位壓控振盪器。第四章為使用第三章所提出的X頻段汲極端電容耦合F23類四相位壓控振盪器作為振盪源實現的X頻段F23類四相位鎖相迴路。
第二章為K/Ka頻段使用開關電容陣列和可開關式可變電容陣列之5位元壓控振盪器。前半部分主要介紹多位元開關電容陣列和可開關式可變電容陣列的設計分析，首先提及KVCO對相位雜訊及鎖相迴路穩定性的影響，帶出KVCO小的情況下要使用開關電容陣列才能夠維持高可調範圍，又因為KVCO小所以有額外設計輔助用可開關式可變電容，確保頻率的連續性。電路架構為最基本的交錯耦合對搭配5位元的開關電容陣列及可開關式可變電容陣列實現一壓控振盪器，此電路使用台積電90 nm CMOS製程實現，可調頻率範圍為22.6~29.8 GHz(27.5%)，整體輸出功率為-6~-7.7 dBm，整體距載波偏移1 MHz相位雜訊在-98~-103.5 dBc/Hz，FoMPN為-184~-184.4 dBc/Hz，FoMT為-192.8~-193.1 dBc/Hz，晶片面積為0.94 × 0.81 mm2。第二章後半部分則是著重說明如何依照業界設計需求，經由經驗及公式計算快速設計位元數，並使用台積電22 nm CMOS製程舉出模擬實例。
第三章為X頻段之F23類四相位壓控振盪器，由時變模型，我們知道要將輸出波形整型成方波才能夠得到較好的相位雜訊，即F類壓控振盪器。又因為Groszkowski effect，所以我們知道要在二倍頻做一個高阻抗降低波形的不對稱性，以此得到較好的相位雜訊，於是最終選擇實作F23類壓控振盪器。首先設計F23類差動壓控振盪器，接著再根據設計完的差動壓控振盪器搭配背閘極耦合、閘極端電容耦合和汲極端電容耦合的方式，實作出F23類四相位壓控振盪器。本章節之電路皆是使用台積電0.18 μm CMOS製程實現，經過量測比較後，我們得知使用汲極端電容耦合的F23類四相位壓控振盪器有較好的電路性能，其可調頻率範圍為10.23~10.89 GHz，整體輸出功率在-6~-8 dBm，整體距離載波偏移1 MHz的相位雜訊在-110.5 ~ -113.8 dBc/Hz，最小的相位誤差以及振幅誤差分別是0.3°和0.1 dB，FoMPN為-181.1 ~ -184.5 dBc/Hz，FoMT為-176.8 ~ -180.2 dBc/Hz，FoMQ約為-202~-228.7 dBc/Hz，晶片面積為0.725 × 1.127 mm2。
第四章為X頻段之F23類四相位鎖相迴路，本章將介紹鎖相迴路的每個子電路之功能及如何運作，接著再分析鎖相迴路的穩定性及突波抑制能力，迴路中的壓控振盪器使用第三章的汲極端電容耦合F23類四相位壓控振盪器。本章節之電路使用台積電0.18 μm CMOS製程實現，壓控振盪器本身的頻率可調範圍為10.51~11.06 GHz，而鎖相迴路之頻率鎖定範圍為10.52~11.06 GHz，幾乎全頻段鎖定，距離載波偏移1 MHz的相位雜訊為−104 dBc/Hz，量測到的最小方均根抖動量為250 fs，抖動的積分範圍為1 kHz到40 MHz。全頻段的突波抑制量皆大於60 dBc，鎖相迴路部分的FoMPN為-166.5 dBc/Hz，FoMjitter為-233.7 dB，FoMN為-251.7 dB，晶片面積為1.05 × 1.614 mm2。
;This paper primarily investigates the use of a switched-capacitor array and waveform shaping to achieve a local oscillator with lower phase noise. Chapter 2 focuses on a K and Ka-band voltage-controlled oscillator (VCO) using a 5-bit switch-capacitor array to achieve high frequency tuning range. Chapter 3 first discusses the impact of waveform shaping on phase noise, and introduces X-band Class-F23 voltage-controlled oscillator. Additionally, it proposes three ways to realize Class-F23 quadrature voltage-controlled oscillators(QVCO), each utilizing back-gate coupling, gate capacitance coupling, and drain capacitance coupling, respectively. Chapter 4 focuses on implementing an X-band Class-F23 quadrature phase-locked loop (PLL) using the X-band quadrature voltage-controlled oscillator with drain capacitance coupling as the oscillator source in Chapter 3.
Chapter 2 is talking about a K/Ka-band 5-bit VCO, which using switch-capacitor array and switchable varactor array. The first half of chapter primarily focuses on the design of multi-bit switch-capacitor arrays and switchable varactor array. First, it metions the impact of the KVCO on phase noise and phase-locked loop stability. When the KVCO is small, the utilization of a switch-capacitor array becomes necessary to maintain a high tuning range, additionally, due to the small KVCO, so I designed auxiliary switchable varactor to ensure frequency continuity. The circuit topology is the fundamental cross-coupled pair with 5-bit switch-capacitor array and switchable varactor array to realize a voltage-controlled oscillator. This circuit is fabricated in TSMC 90 nm CMOS process. The frequency tuning range is from 22.6 to 29.8 GHz(27.5%), the overall output power is from -6 to -7.7 dBm, the overall phase noise at 1 MHz offset frequency is from -98 to -103.5 dBc/Hz, the FoMPN is from -184 to -184.4 dBc/Hz, the FoMT is from -192.8 to -193.1 dBc/Hz, the chip size is 0.94 × 0.81 mm2. The second half of Chapter 2 focuses on explaining how to design bit numbers quickly according to industry design specifications, using experience and formula calculations. It also provides a simulated example using TSMC 22 nm CMOS process.
Chapter 3 is about the design of an X-band Class-F23 quadrature voltage-controlled oscillator. From the time-variant model, we know that shaping the output waveform into a square wave is necessary to achieve better phase noise, which corresponds to an Class-F voltage-controlled oscillator. Additionally, due to the Groszkowski effect, we need to realize a high-impedance at twice the frequency to reduce waveform asymmetry and improve phase noise. Therefore, the final choice is to implement the Class-F23 voltage-controlled oscillator. First, we design a Class-F23 voltage-controlled oscillator. Then, based on the designed voltage-controlled oscillator, we implement a quadrature voltage-controlled oscillator of the Class-F23 using methods such as back-gate coupling, gate capacitance coupling, and drain capacitance coupling, respectively. This circuit is fabricated in TSMC 0.18 μm CMOS process. After the measurment and comparison, we know that the Class-F23 quadrature voltage-controlled oscillator with drain capacitance coupling exhibited better circuit performance. The frequency tuning range is from 10.23 to 10.89 GHz, the overall output power is from -6 to -8 dBm, the overall phase noise at 1 MHz offset frequency is from -110.5 to -113.8 dBc/Hz,the FoMPN is from -181.1 to -184.5 dBc/Hz, the FoMT is from -176.8 to -180.2 dBc/Hz, the FoMQ is from -202 to -228.7 dBc/Hz, the chip size is 0.725 × 1.127 mm2.
Chapter 4 introduces the X-band Class-F23 quadrature phase-locked loop. This chapter will discuss the functions and operating theory of each sub-circuit in the PLL. Furthermore, it will analyze the stability and spur suppression ability of the PLL. The voltage-controlled oscillator in the loop utilizes the quadrature voltage-controlled oscillator with drain capacitance coupling which introduced in Chapter 3. This circuit is fabricated in TSMC 0.18 μm CMOS process. The VCO frequency tuning range is from 10.51 to 11.06 GHz,and the PLL frequency locking range is from 10.52 to 11.06 GHz, almost full frequncy band locking, the phase noise at 1 MHz offset frequency is -104 dBc/Hz. Under the integration range of 1 kHz to 40 MHz, the measured minimum root mean square jitter is 250 fs. The spur suppression throughout the entire frequency band is greater than 60 dBc. The FoMPN is -166.5 dBc/Hz, the FoMjitter is -233.7 dB, the FoMN is -251.7 dB, the chip size is 1.05 × 1.614 mm2. |
