使用串接次諧波注入鎖定鎖頻迴路鏈實現Ka頻段1024-QAM正交調變器之研製;Research on Ka-Band 1024-QAM I/Q Modulator Using Cascade Sub-Harmonically Injection-Locked Frequency-Locked Loop Chain

NCU Institutional Repository > 資訊電機學院 > 電機工程研究所 > 博碩士論文 > Item 987654321/95596

請使用永久網址來引用或連結此文件: http://ir.lib.ncu.edu.tw/handle/987654321/95596

題名:	使用串接次諧波注入鎖定鎖頻迴路鏈實現Ka頻段1024-QAM正交調變器之研製;Research on Ka-Band 1024-QAM I/Q Modulator Using Cascade Sub-Harmonically Injection-Locked Frequency-Locked Loop Chain
作者:	陳良宇;Chen, Liang-Yu
貢獻者:	電機工程學系
關鍵詞:	鎖頻迴路;四相位壓控振盪器;正交調變器;次諧波注入鎖定;Frequency-Locked Loop;Quadrature Voltage Control Oscillator;I/Q Modulator;Sub-Harmonically Injection-Locked
日期:	2024-07-09
上傳時間:	2024-10-09 17:05:19 (UTC+8)
出版者:	國立中央大學
摘要:	本篇論文研究使用注入鎖定技術應用於振盪器及鎖頻迴路，並與正交調變器做整合。第二章為操作在X頻段的脈衝振盪器，第三章為使用脈衝振盪器實現之Ka頻段九倍次諧波注入鎖定I/Q調變器，第四章為使用15th倍注入鎖定倍頻器鏈實現之Ka頻段I/Q調變器。本篇論文的設計皆使用TSMC 90 nm GUTM CMOS製程實現。第二章將介紹脈衝振盪器的設計，透過比較方波注入與一般使用弦波注入帶來的諧波電流改善做出了分析，同時也對鎖定範圍進行了比較。量測到之鎖定頻寬為8.1 GHz至11.11 GHz，相位雜訊距載波偏移1 MHz最低為-131.8 dBc/Hz，直流功率消耗為12.3 mW，晶片面積為0.49 mm2。第三章採用了脈衝振盪器串接注入鎖定正交鎖頻迴路整合正交調變器，這個章節會介紹以及分析鎖頻迴路的各個子電路以及使用梅森理論來分析迴路的相位雜訊，並接著與正交調變器做整合。量測鎖頻迴路之鎖定頻寬為25.84 GHz至27.1 GHz，相位雜訊距載波偏移1 MHz為-120 dBc/Hz，抖動量積分範圍由1 kHz到40 MHz最小為36 fs，晶片面積為1.74 mm2，由於鎖頻迴路具有低抖動、低相位雜訊和低正交誤差的特性，因此在操作頻率25.9 GHz至27.1 GHz之間，量測到之EVM皆小於3％，並且調變方案最高可以達到256-QAM，最終在FoM的表現突出。第四章是第三章電路的改良版本，改良部分由原本的單端注入路徑改良成雙端注入路徑，透過理論分析與模擬驗證雙端注入帶來的好處與設計考量，而整個15th倍頻器鏈是由一個五倍的差動鎖頻迴路串接三倍的正交鎖頻迴路組合而成。量測鎖頻迴路之鎖定頻寬為27 GHz到28.7 GHz，相位雜訊距載波偏移1 MHz為-121.8 dBc/Hz，抖動量積分範圍由1 kHz到40 MHz最小為30.8 fs，晶片面積為2.16 mm2，由於雙端注入帶來的有效改善，因此在操作頻率27 GHz至28.7 GHz之間，量測到之EVM皆小於2％，並且調變方案最高可以達到1024-QAM，最終在FoM的表現上優於第三章之電路。 ;The paper investigates the application of injection-locked techniques in oscillators and frequency-locked loops integrated with I/Q modulators. Chapter two deals with pulse oscillators operating in X-band. Chapter three discusses the implementation of a ninefold sub-harmonically injection-locked I/Q modulator using pulse oscillator in Ka-band. Chapter four presents a Ka-band I/Q modulator realized using a 15th-order sub-harmonically injection-locked frequency multiplier chain. All designs are implemented using 90-nm CMOS process provided by TSMC. Chapter two will introduce the design of pulse oscillator. Through analysis, it not only compares the improvement in harmonic current drown by pulsed injection with the one using sinewave injection, it also compares the locking ranges. The measured locking range is from 8.79 GHz to 9.25 GHz, with the lowest phase noise at 1-MHz offset of -131.8 dBc/Hz. The dc power consumption is 12.3 mW, and the chip size is 0.49 mm2. Chapter three adopts a pulse oscillator followed by a sub-harmonically injection-locked quadrature frequency-locked loop integrated with an I/Q modulator. This chapter will introduce and analyze various sub-circuits of the frequency-locked loop and use Mason′s rule to analyze the phase noise of the loop. Subsequently, it integrates with the I/Q modulator. The measured locking range of the frequency-locked loop is from 25.84 GHz to 27.1 GHz, with a phase noise of -120 dBc/Hz at 1-MHz offset. The minimum rms jitter integrated from 1 kHz to 40 MHz is 36 fs, and the chip size is 1.74 mm2. Due to the low jitter, low phase noise, and low quadrature error characteristics of the frequency-locked loop, the measured EVM is less than 3% in the operating frequency range from 25.9 GHz to 27.1 GHz. Moreover, the modulation scheme is up to 256-QAM, demonstrating an outstanding performance in figure-of-merit (FoM). Chapter four presents an improved version of the circuit from chapter three. The improvement involves replacing the original single-ended injection path with a differential injection path. The benefits and design considerations of the differential injection are analyzed through theoretical analysis and simulation verification. The entire 15th-order multiplier chain is composed of a 5th-order differential frequency-locked loop and a 3rd-order quadrature frequency-locked loop. The measured locking range of the frequency-locked loop is from 27 GHz to 28.7 GHz, with a phase noise of -121.8 dBc/Hz at 1-MHz offset. The minimum rms jitter integrated from 1 kHz to 40 MHz is 30.8 fs, and the chip size is 2.16 mm2. Due to the effective improvement by the differential injection, the measured EVM is less than 2% in the operating frequency range from 27 GHz to 28.7 GHz. Moreover, the modulation scheme is up to 1024-QAM, demonstrating a superior performance in FoM compared to the circuit in chapter three.
顯示於類別:	[電機工程研究所] 博碩士論文

文件中的檔案:

檔案	描述	大小	格式	瀏覽次數
index.html		0Kb	HTML	15	檢視/開啟

在NCUIR中所有的資料項目都受到原著作權保護.

社群 sharing

資料載入中.....