基於負載均衡的脈動陣列老化效應緩解達到可靠性提升設計;Mitigating Aging Effects in Systolic Arrays: A Load Balancing Approach for Reliability Improvement

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Title:	基於負載均衡的脈動陣列老化效應緩解達到可靠性提升設計;Mitigating Aging Effects in Systolic Arrays: A Load Balancing Approach for Reliability Improvement
Authors:	何宜真;Ho, Yi-Chen
Contributors:	電機工程學系
Keywords:	脈動陣列;老化效應;人工智慧加速器;Systolic array;Aging effect;AI accelerator
Date:	2024-07-16
Issue Date:	2024-10-09 17:06:45 (UTC+8)
Publisher:	國立中央大學
Abstract:	基於脈動陣列的加速器被認為是用於深度神經網絡（DNN）加速數據密集型神經網絡計算的最有前途的架構之一，然而脈動陣列的固定大小可能導致顯著的工作負載不平衡，處理單元（PEs）的利用率可能會有很大的差異，在脈動陣列中的PEs最大和最小使用率之間的差異可能高達14倍。此外老化效應，例如熱載流子注入（HCI）和偏壓溫度不穩定性（BTI），可能會隨著時間的推移引入時序錯誤或功能故障，特別是在高使用率的PEs中，最終由於高負載PEs上的老化效應，整個脈動陣列的壽命可能會縮短。針對這些挑戰，本文介紹了一種創新的老化感知脈動陣列設計框架，該框架包括兩個關鍵步驟——平衡負載的脈動陣列數據路徑設計和老化感知的數據映射策略——緩解因老化引起精度下降的方針。實驗表明，在經歷十年的老化後，我們的系統在預測精度上比傳統的基於脈動陣列的AI加速器提高了60.7%，同時我們的方法可以將脈動陣列的利用率提高至2.4倍。;The systolic-array-based accelerator stands out as one of the most promising architectures for deep neural network (DNN) acceleration in data-intensive neural network computation. Nevertheless, the fixed size of the systolic array can result in significant workload imbalances, leading to considerable variations in the utilization rates of processing elements (PEs). This discrepancy can reach up to a x14 difference between the maximum and minimum usage. Furthermore, aging effects, such as Hot Carriers Injection (HCI) and Bias Temperature Instability (BTI), can introduce timing errors or functional failures over time, particularly in PEs with high usage. Consequently, the lifespan of the entire systolic array can be shortened due to aging effects on heavily utilized PEs. In response to these challenges, this paper introduces an innovative aging-aware systolic array design framework. Comprising two key components - a balance-loaded systolic array datapath design and an aging-aware data mapping policy - this framework aims to alleviate the aging-induced accuracy degradation. Experiments show that, after ten years of aging, our system can achieve a prediction accuracy improvement of 60.7% over a traditional systolic-array-based AI accelerator. Our approach can increase utilization up to 2.4 times in the meantime.
Appears in Collections:	[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

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