| 摘要: | 由於半導體發展隨著摩爾定律，算力提升、能耗下降與製作成本降低，使人類社會對電力設備的應用更加創新，當晶片與電路板足夠小，設備續航力足夠且價格大多數人可以接受時，就到達科技發展的奇異點，即第四次工業革命。主要著重於穿戴設備的互聯性、電子產品自動化、機械學習和即時數據傳輸等方面。藉由演算法和控制工程機械等設備實現自動化監測和數據分析，思維突破進而創新。
近年來的工業控制設備中，如工業自動化逆變器，交流伺服馬達控制器，用於再生能源的功率調節器等應用，都需要隔絕兩側電壓電源以確保設備的安全性。其中晶片裡的隔離放大器就格外重要，要考慮其傳輸速度、消耗功率與最高隔絕電壓，本文以整體系統制定傳輸速度，隔離元件製作於晶片內部減少面積，降低消耗功率為目標。
本論文實現應用於磁耦合隔離系統，電路架構主要分為兩部分，基於變壓器的磁耦合數位隔離放大器與時脈資料回復電路，數位隔離放大器以Pulse Polarity為基礎架構，具有較小變壓器面積與較低功耗的優勢，細部電路架構有邊緣檢測器(Edge Dectetor)檢測正緣與負緣，限流反向器(Current Limiting Inverter)去抑制會造成邏輯錯亂的反向波，Metal 6與Metal 4 的螺旋電感(Spiral Inductor)堆疊成變壓器，用集總電路(Lump circuit)的方式去分析變壓器的寄生，再以高速脈衝檢測器與比較器將數位訊號還原；時脈資料回復電路(Clock Data Recovery)細部架構包含，相位檢測器(Phase Detector)、充電泵(Charge Pump)、迴路濾波器(Loop Filter)和電壓控制震盪器(Voltage Control Oscillator)，在相對低速的環境，選擇Hogge 相位檢測器以符合需求，採用雙路徑充電泵的迴路濾波器以降低濾波器中電容元件的面積。
本電路採用台積電0.18μm CMOS 1P6M製程，晶片面積約佔0.810 mm2，電源供應電壓為1.8 V，整體電路功耗為21.83 mW，電路傳輸速度為28.8Mbps，電感直徑為276 μm，隔離電壓值為170 V，瞬態共模噪音抑制 (CMTI)為35 kV/μs，鎖定時間為24.2 μs，時脈抖動為28.12 ps。
;With the advancement of semiconductor technology driven by Moore′s Law, computational power has increased, energy consumption has decreased, and manufacturing costs have been reduced. These developments have led to innovative applications of electrical equipment in human society. When chips and circuit boards become sufficiently small, devices achieve adequate battery life, and prices become affordable to the majority, the technological singularity of development—namely the Fourth Industrial Revolution—is reached. This revolution focuses on the interconnectivity of wearable devices, automation of electronic products, machine learning, and real-time data transmission. Through algorithms, control engineering, and mechanical systems, automation monitoring and data analysis are realized, breaking traditional boundaries and fostering innovation.
In recent years, industrial control equipment, such as industrial automation inverters, AC servo motor controllers, and power regulators for renewable energy, has increasingly required isolation between voltage sources on both sides to ensure equipment safety. Among these components, isolation amplifiers embedded in chips play a critical role. These amplifiers must balance considerations of transmission speed, power consumption, and maximum isolation voltage. This thesis sets the transmission speed based on the overall system, integrates the isolation components within the chip to reduce area, and aims to minimize power consumption.
This thesis implements a circuit architecture for magnetic coupling isolation systems, primarily consisting of two parts: a transformer-based magnetically coupled digital isolation amplifier and a clock data recovery (CDR) circuit. The digital isolation amplifier is based on the pulse polarity architecture, offering advantages such as smaller transformer area and lower power consumption. The detailed circuit design includes edge detectors for detecting rising and falling edges, current-limiting inverters to suppress counter-pulses that may cause logic errors, and a transformer constructed by stacking spiral inductors using Metal 6 and Metal 4 layers. A lumped circuit model is employed to analyze the transformer′s parasitics, while high-speed pulse detectors and comparators are used to recover digital signals.
The CDR circuit comprises a phase detector, charge pump, loop filter, and voltage-controlled oscillator (VCO). For relatively low-speed environments, a Hogge phase detector is adopted to meet the requirements, and a dual-path charge pump loop filter is utilized to reduce the area of the capacitive components within the filter.
The circuit is fabricated using TSMC’s 0.18 μm CMOS 1P6M process, with a chip area of approximately 0.810 mm². The supply voltage is 1.8 V, and the total circuit power consumption is 21.83 mW. The circuit achieves a transmission speed of 28.8 Mbps, with an inductor diameter of 276 μm, an isolation voltage of 170 V, transient common-mode noise immunity (CMTI) of 35 kV/μs, a lock time of 24.2 μs, and clock jitter of 28.12 ps. |
