本研究以A公司為例，探討如何結合限制理論（Theory of Constraints, TOC）與精實生產（Lean Production）方法，改善半導體封裝測試製程中捲帶包裝站的瓶頸問題。隨著人工智慧（Artificial Intelligence, AI）應用日益擴展，半導體產業面臨需求攀升與小量多樣生產挑戰，傳統擴產策略已難以有效因應市場變動，因此提升既有產線之效率與彈性成為當務之急。 本研究首先應用TOC三大核心問題與五大改善步驟，識別捲帶製程中的瓶頸站點，並透過DBR（Drum-Buffer-Rope）排程方法建立以瓶頸為核心的生產節奏，縮短生產週期時間（Cycle Time）、降低在製品（Work in Process, WIP）。隨後運用六標準差之DMAIC（Define-Measure-Analyze-Improve-Control）改善方法，透過價值溪流圖（Value Stream Mapping, VSM）與特性要因圖，分析出主要浪費來源，並提出相對應具體改善措施。 實證結果顯示，瓶頸站WIP量降低25%、生產週期縮短18%。本研究證實TOC與精實生產結合應用於半導體捲帶包裝製程具可行性與實效性，並提供產線改善與自動化導入之具體建議，對同類型產線具有高度實務參考價值與管理意涵。 ;This study investigates the integration of the Theory of Constraints (TOC) and Lean Production to address bottlenecks in the tape-and-reel packaging process of semiconductor final testing, using Company A as a case study. With the rapid expansion of Artificial Intelligence (AI) applications, the semiconductor industry faces growing demand and increasing complexity from high-mix, low-volume production, making efficiency and flexibility in existing production lines more critical than ever. The study applies TOC’s three core questions and five focusing steps to identify and address the primary bottleneck. A production rhythm centered on the constraint is established through the Drum-Buffer-Rope (DBR) scheduling method. The six-sigma DMAIC methodology is then used, incorporating Value Stream Mapping (VSM) and cause-and-effect diagrams to identify major sources of waste and implement targeted improvement measures. Empirical results show a 25% reduction in WIP and an 18% reduction in production cycle time. The study demonstrates the feasibility and effectiveness of combining TOC and Lean approaches and provides actionable recommendations for production improvement and automation in similar semiconductor manufacturing environments.
