| 摘要: | 摘要
隨著半導體製程邁向更高精度與更小尺寸節點，製程中各環節的穩定性與良率管控成為產業競爭的核心關鍵。臨時貼合（Temporary Bonding）技術作為晶圓薄化與後段封裝製程的重要支撐工藝，廣泛應用於3D IC、Fan-Out WLP等先進封裝場景。然而，臨時貼合過程涉及膠層厚度、壓力、溫度、間隙與時間等多重參數交互影響，若未能妥善調控，將導致貼合強度不足、晶圓破片、氣泡殘留或界面翹曲等缺陷，進而降低製程良率並造成生產停滯。
本研究以某美商半導體設備廠於新竹所設製造中心為實證個案，導入田口品質工程方法，針對實際量產設備之臨時貼合製程進行參數優化。透過田口直交表L₁₆(4⁴×2²)安排六個關鍵控制因子與其水準組合，並以實驗量測方式取得貼合強度值作為品質特性，以「望大特性」之S/N比進行統計分析與主因子篩選。研究結果顯示，貼合間隙（預壓距離）與膠層厚度對接合強度有最顯著影響，為主要優化對象。經驗證實驗確認，最佳參數組合下平均S/N比提升至48.57 dB，相較原始設定提升超過10.5%，製程良率由99.21%提升至99.88%，報廢數由月均6件降至3件以下，成效明顯。進一步分析顯示，透過參數標準化與設定最佳化，不僅可穩定貼合品質與提升量產效率，更可降低人為差異與設備誤差對製程穩定性的影響。估算每年可節省報廢重工人力、工程調機與物料處理成本達新台幣870萬元，對於中小型生產線而言已具相當規模的經濟效益。本研究亦證明田口方法可作為半導體臨時貼合製程中跨部門協同優化的重要工具，不僅適用於既有平台參數優化，更具潛力擴展至異質結合、激光脫附與多層貼合等複雜製程場景，為提升製程韌性與量產穩定性提供系統化支援。
;Abstract
As semiconductor manufacturing evolves toward finer nodes and higher complexity, process stability and yield optimization become critical in maintaining competitive advantages. Temporary wafer bonding has emerged as a key enabler in advanced packaging processes such as 3D ICs and Fan-Out Wafer-Level Packaging (FO-WLP). However, the bonding process involves multiple interacting parameters—including adhesive thickness, bonding gap, applied pressure, temperature, and dwell time—any of which can significantly impact bond quality. Insufficient bonding strength may lead to wafer cracking, delamination, or warping, resulting in yield loss and production downtime.
This study adopts the Taguchi Method to optimize temporary bonding process parameters in a real-world manufacturing environment. A case study was conducted at a U.S.-based semiconductor equipment company operating its Asia manufacturing hub in Hsinchu, Taiwan. Using a Taguchi L₁₆(4⁴×2²) orthogonal array, six key bonding parameters were selected for experimentation. Peel strength was chosen as the response characteristic, and the larger-the-better Signal-to-Noise (S/N) ratio was applied to evaluate robustness under different parameter combinations. Experimental results showed that the pre-bonding gap and adhesive thickness had the most significant influence on bonding strength. The optimal parameter combination resulted in an average S/N ratio of 48.57 dB, a 10.5% improvement over the baseline configuration. Yield increased from 99.21% to 99.88%, and monthly wafer scrap counts were reduced by over 50%. Cost savings from reduced rework, labor hours, and material waste were estimated at over NTD 8.7 million annually. Furthermore, by standardizing bonding parameters and minimizing process drift, the optimization helped reduce operator variability and improved cross-department alignment in equipment setup and troubleshooting. The study confirms that the Taguchi Method is highly effective for process parameter optimization in semiconductor packaging environments. Its statistical rigor and reduced experiment count make it suitable for real-world production scenarios where time and resource constraints are common. The framework developed in this study can be extended to other bonding applications, including heterogeneous integration, laser debonding, and multilayer stack processes. It also provides a foundation for integrating robust design principles into intelligent manufacturing systems such as digital twins and AI-assisted process control, thereby supporting continuous improvement and long-term competitiveness in the semiconductor industry. |
