應用邏輯迴歸模型分析晶圓測試廠測試報表錯誤的關鍵因子-以A公司為例;Applying Logistic Regression Models to Analyze Key Factors of Causing Wafer Map Error in a Testing House－A Case Study of Company A.

NCUIR > School of Management at National Central University > Executive Master of Industrial Management > Electronic Thesis & Dissertation > Item 987654321/97330

Please use this identifier to cite or link to this item: https://ir.lib.ncu.edu.tw/handle/987654321/97330

Title:	應用邏輯迴歸模型分析晶圓測試廠測試報表錯誤的關鍵因子-以A公司為例;Applying Logistic Regression Models to Analyze Key Factors of Causing Wafer Map Error in a Testing House－A Case Study of Company A.
Authors:	林駿鴻;Lin, Chun-hung
Contributors:	工業管理研究所在職專班
Keywords:	晶圓測試廠;測試報表;邏輯迴歸;wafer testing house;wafer map;logistic regression
Date:	2025-07-24
Issue Date:	2025-10-17 11:08:51 (UTC+8)
Publisher:	國立中央大學
Abstract:	半導體產業在台灣已經有50年的歷史，且在半導體產業也取得多項成就，除了上游的IC設計廠聯發科，中游的護國神山台積電、聯電，下游的封裝測試廠日月光、艾克爾。而周邊支持整個半導體產業的供應鏈也是相當完整。故讓台灣有半導體王國的美名。而下游中大大小小的封裝測試廠更是超過50家，可說是百家爭鳴。其中測試廠更是更是大部分決定要把生意放在哪間封裝廠的依據之一。有別於其他代工廠生態，測試廠並不算製造業而比較像是「服務業」的存在，因為測試廠最重要的產出是一份測試報表，所以提供一份正確的測試報表則是測試廠最重的工作，本研究旨在探討晶圓測試廠測試報表錯誤的關鍵影響因子，以提升測試報表品質與確保資訊的正確性。透過蒐集A公司之實際測試報表資料，運用邏輯迴歸（Logistic Regression）模型進行分析，篩選出與報表被檢查出是錯誤的顯著相關的可控變數。研究結果顯示，材料流水號與測試程式輸入的設定為影響測試報表被檢出是錯誤率的主要因素。最後，根據分析結果提出改善建議，有助於強化測試報表管理機制，提升生產效率與資料正確性。;Taiwan has a 50-year history in the semiconductor industry and has achieved significant accomplishments across the value chain, including upstream IC design house like MediaTek, midstream foundries such as TSMC and UMC, and downstream assembly and testing house like ASE and Amkor. The surrounding supply chain that supports the entire semiconductor ecosystem is also well-developed, earning Taiwan the reputation of being a “semiconductor kingdom.” In the downstream sector, there are more than 50 assembly and testing houses of varying sizes, creating a highly competitive environment. Among them, wafer testing houses often play a decisive role in determining which assembly house will ultimately win the business. Unlike OEM, wafer testing houses function more like service providers, as their most critical deliverable is the wafer map(inkless map). Therefore, providing an accurate wafer map is crucial to their operation. This study aims to identify the key factors that lead to wafer map errors in a wafer testing house, thereby improving wafer map quality and ensuring data accuracy. Using actual wafer map data from Company A, this research applies a logistic regression model to analyze and identify significant controllable variables associated with report errors. The results reveal that Wafer runcard# settings and test program settings are the primary factors influencing the error rate. Based on these findings, the study proposes practical recommendations to strengthen test report management, enhance production efficiency, and improve data accuracy.
Appears in Collections:	[Executive Master of Industrial Management] Electronic Thesis & Dissertation

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