隨著非地面網路 (NTN) 與低軌道衛星通訊系統的蓬勃發展，如何在有限資源與高 動態環境中實現穩定且高效的數位基頻通訊模組成為關鍵課題。為因應衛星任務對低 延遲、高頻寬與模組化設計的需求，本研究提出一套符合DVB-S2標準之數位收發機 架構，並以FPGA為核心實現系統設計。 藉由Zynq SoC 結合AD9361 RF前端，構建出完整的SDR平台。發射端訊號以自 行設計之DVB_DM1訊號模組為主，支援不同 Oversampling Ratio (OVSR) 配置以模 擬變化頻寬場景；接收端則透過 ILA、DMA與 PYNQ平台實現即時資料回收與後端 數位訊號處理。系統最終成功整合並實驗於3U立方衛星「Nightjar」通訊酬載中。此 外也整合UHF次系統，並通過包含熱真空、振動、輻射等環境測試驗證。並且實驗結 果顯示本系統在短距與20公尺OTA對傳中皆可達成低於10%的誤差向量幅度 (EVM)，證實本設計架構具備實用性與高度可擴展性，為實現B5G衛星通訊模組提供 具體實作方案與驗證依據。;With the emergence of Non-Terrestrial Networks (NTN) and Low Earth Orbit (LEO) satellite systems, the development of efficient and robust digital baseband architecture has become essential. This study presents an FPGA-based DVB-S2 compliant digital transceiver architecture for satellite communication payloads. The system integrates a Zynq SoC and AD9361 RF front-end to form a complete SDR platform. A custom DVB_DM1 module is designed to support variable oversampling ratios, simulating diverse bandwidth scenarios. The receiver incorporates ILA, DMA, and PYNQ for real-time data capture and backend processing. The architecture is implemented and verified on the 3U CubeSat “Nightjar,” alongside a UHF subsystem. Environmental validation including thermal vacuum, vibration, and radiation tests was conducted. Experimental results confirm that the system achieves error vector magnitude (EVM) below 10% in both short-range and 20-meter OTA transmission, demonstrating its practicality and scalability for future B5G satellite applications.
