在現今數位化的時代，對於資料傳輸的需求遽增，高容量與高速數據傳輸逐漸成為生活中的日常所需，數位化的到來，帶動著資料中心、高效能運算與雲端服務的迅速發展，對於高速資料傳輸介面的需求大幅提升，過往SerDes採用的NRZ（Non-Return-to-Zero, NRZ）調變技術已無法滿足112Gbps以上的資料速率傳輸需求，因此對於超高速數據傳輸逐步朝向 PAM4(四階脈衝振幅調變，Pulse Amplitude Modulation 4-level, PAM-4）調變技術發展。在相同的資料速率下，PAM4可以傳輸的資料量為NRZ的兩倍，因此PAM4成為達成224Gbps資料速率的關鍵技術之一，然而高速的資料傳輸速率，對於整體傳輸訊號的頻寬規格標準也日漸提升。 本論文研究針對PAM4 224Gbps高速晶片最終測試(FT，Final Test)需求中的Test Socket進一步研究開發，並建立一套可驗證Test Socket本身特性的超寬頻驗證架構，透過HSFF軟體進行設計後，使用110GHz向量網路分析儀(VNA，Vector Network Analyzer)進行S參數量測確認頻寬特性和時域反射儀(TDR，Time Domain Reflectometry)確認其阻抗特性。 ;In today’s digital era, the demand for data transmission has surged significantly, making high-capacity and high-speed data transfer an essential part of everyday life. The advancement of digitalization has driven the rapid development of data centers, high-performance computing, and cloud services, leading to a substantial increase in the demand for high-speed data transmission interfaces. The traditional NRZ (Non-Return-to-Zero) modulation technique used in SerDes architectures is no longer sufficient to support data rates exceeding 112 Gbps. As a result, ultra-high-speed data transmission is rapidly shifting toward PAM4 (Pulse Amplitude Modulation 4-level) technology. At the same symbol rate, PAM4 can transmit twice the amount of data compared to NRZ, making it a key technology for achieving 224 Gbps data rates. However, higher transmission speeds also impose increasingly stringent signal bandwidth requirements.
This thesis focuses on the development of a Test Socket tailored for Final Test (FT) requirements of PAM4 224 Gbps high-speed chips. A comprehensive ultra-broadband validation framework is established to characterize the performance of the Test Socket. The socket is designed using HSFF software, with bandwidth characteristics verified through S-parameter measurements using a 110 GHz Vector Network Analyzer (VNA), and impedance characteristics validated using Time Domain Reflectometry (TDR).
